1// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6
7//     http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15
16#include <xtensa/coreasm.h>
17#include <xtensa/corebits.h>
18#include <xtensa/config/system.h>
19#include "freertos/xtensa_context.h"
20#include "esp_private/panic_reason.h"
21#include "sdkconfig.h"
22#include "soc/soc.h"
23#include "soc/dport_reg.h"
24
25/*
26
27Interrupt , a high-priority interrupt, is used for several things:
28- Cache error panic handler
29- Interrupt watchdog panic handler
30
31*/
32
33    .section .iram1,"ax"
34    .global     xt_highint4
35    .type       xt_highint4,@function
36    .align      4
37xt_highint4:
38
39    /* Allocate exception frame and save minimal context. */
40    mov     a0, sp
41    addi    sp, sp, -XT_STK_FRMSZ
42    s32i    a0, sp, XT_STK_A1
43    #if XCHAL_HAVE_WINDOWED
44    s32e    a0, sp, -12                     /* for debug backtrace */
45    #endif
46    rsr     a0, PS                          /* save interruptee's PS */
47    s32i    a0, sp, XT_STK_PS
48    rsr     a0, EPC_4                       /* save interruptee's PC */
49    s32i    a0, sp, XT_STK_PC
50    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
51    s32i    a0, sp, XT_STK_A0
52    #if XCHAL_HAVE_WINDOWED
53    s32e    a0, sp, -16                     /* for debug backtrace */
54    #endif
55    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
56    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
57    call0   _xt_context_save
58
59    /* Save vaddr into exception frame */
60    rsr     a0, EXCVADDR
61    s32i    a0, sp, XT_STK_EXCVADDR
62
63    /* Figure out reason, save into EXCCAUSE reg */
64
65    rsr     a0, INTERRUPT
66    extui   a0, a0, ETS_MEMACCESS_ERR_INUM, 1 /* get cacheerr int bit */
67    beqz    a0, 1f
68    /* Kill this interrupt; we cannot reset it. */
69    rsr     a0, INTENABLE
70    movi    a4, ~(1<<ETS_MEMACCESS_ERR_INUM)
71    and     a0, a4, a0
72    wsr     a0, INTENABLE
73    movi    a0, PANIC_RSN_CACHEERR
74    j 9f
751:
76    /* Set EXCCAUSE to reflect cause of the wdt int trigger */
77    movi    a0,PANIC_RSN_INTWDT_CPU0
789:
79    /* Found the reason, now save it. */
80    s32i    a0, sp, XT_STK_EXCCAUSE
81
82    /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
83    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
84    wsr     a0, PS
85
86    //Call panic handler
87    mov     a6,sp
88    call4   panicHandler
89
90    call0   _xt_context_restore
91    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
92    wsr     a0, PS
93    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
94    wsr     a0, EPC_4
95    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
96    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
97    rsync                                   /* ensure PS and EPC written */
98
99    rsr     a0, EXCSAVE_4                   /* restore a0 */
100    rfi     4
101
102/* The linker has no reason to link in this file; all symbols it exports are already defined
103   (weakly!) in the default int handler. Define a symbol here so we can use it to have the
104   linker inspect this anyway. */
105
106    .global ld_include_highint_hdl
107ld_include_highint_hdl:
108