1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <sys/cdefs.h>
9 // #include <sys/time.h>
10 #include <sys/param.h>
11 #include "sdkconfig.h"
12 #include "esp_attr.h"
13 #include "esp_log.h"
14 #include "esp_cpu.h"
15 #include "esp_clk_internal.h"
16 #include "esp_rom_uart.h"
17 #include "esp_rom_sys.h"
18 #include "soc/system_reg.h"
19 #include "soc/dport_reg.h"
20 #include "soc/soc.h"
21 #include "soc/rtc.h"
22 #include "soc/rtc_periph.h"
23 #include "soc/i2s_reg.h"
24 #include "hal/wdt_hal.h"
25 #include "esp_private/periph_ctrl.h"
26 #include "esp_private/esp_clk.h"
27 // #include "bootloader_clock.h"
28 #include "soc/syscon_reg.h"
29 #include "hal/clk_gate_ll.h"
30
31 static const char *TAG = "clk";
32
33 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
34 * Larger values increase startup delay. Smaller values may cause false positive
35 * detection (i.e. oscillator runs for a few cycles and then stops).
36 */
37 #define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
38
39 #ifdef CONFIG_RTC_XTAL_CAL_RETRY
40 #define RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RETRY
41 #else
42 #define RTC_XTAL_CAL_RETRY 1
43 #endif
44
45 /* Indicates that this 32k oscillator gets input from external oscillator, rather
46 * than a crystal.
47 */
48 #define EXT_OSC_FLAG BIT(3)
49
50 /* This is almost the same as soc_rtc_slow_clk_src_t, except that we define
51 * an extra enum member for the external 32k oscillator.
52 * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values.
53 */
54 typedef enum {
55 SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 90 kHz RC oscillator
56 SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL
57 SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256
58 SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
59 } slow_clk_sel_t;
60
61 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
62
esp_rtc_init(void)63 void esp_rtc_init(void)
64 {
65 rtc_config_t cfg = RTC_CONFIG_DEFAULT();
66 soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0);
67 if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
68 cfg.cali_ocode = 1;
69 /* Ocode calibration will switch to XTAL frequency, need to wait for UART FIFO
70 * to be empty, to avoid garbled output.
71 */
72 if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
73 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
74 }
75 }
76 rtc_init(cfg);
77 }
78
esp_clk_init(void)79 __attribute__((weak)) void esp_clk_init(void)
80 {
81 bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
82 rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
83 rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
84
85 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
86 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
87 // If the frequency changes from 90kHz to 32kHz, then the timeout set for the WDT will increase 2.8 times.
88 // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
89 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
90 // (If frequency is changed from 90kHz to 32kHz then WDT timeout will increased to 1.6sec * 90/32 = 4.5 sec).
91 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
92 uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
93 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
94 wdt_hal_feed(&rtc_wdt_ctx);
95 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
96 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
97 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
98 #endif
99
100 #if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
101 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
102 #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
103 select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
104 #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
105 select_rtc_slow_clk(SLOW_CLK_8MD256);
106 #else
107 select_rtc_slow_clk(SLOW_CLK_RTC);
108 #endif
109
110 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
111 // After changing a frequency WDT timeout needs to be set for new frequency.
112 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000ULL);
113 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
114 wdt_hal_feed(&rtc_wdt_ctx);
115 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
116 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
117 #endif
118
119 rtc_cpu_freq_config_t old_config, new_config;
120 rtc_clk_cpu_freq_get_config(&old_config);
121 const uint32_t old_freq_mhz = old_config.freq_mhz;
122 const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
123
124 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
125 assert(res);
126
127 // Wait for UART TX to finish, otherwise some UART output will be lost
128 // when switching APB frequency
129 if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
130 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
131 }
132
133 if (res) {
134 rtc_clk_cpu_freq_set_config(&new_config);
135 }
136
137 // Re calculate the ccount to make time calculation correct.
138 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
139 }
140
select_rtc_slow_clk(slow_clk_sel_t slow_clk)141 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
142 {
143 #ifdef CONFIG_IDF_ENV_FPGA
144 return;
145 #endif
146 soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
147 uint32_t cal_val = 0;
148 /* number of times to repeat 32k XTAL calibration
149 * before giving up and switching to the internal RC
150 */
151 int retry_32k_xtal = RTC_XTAL_CAL_RETRY;
152
153 do {
154 if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
155 /* 32k XTAL oscillator needs to be enabled and running before it can
156 * be used. Hardware doesn't have a direct way of checking if the
157 * oscillator is running. Here we use rtc_clk_cal function to count
158 * the number of main XTAL cycles in the given number of 32k XTAL
159 * oscillator cycles. If the 32k XTAL has not started up, calibration
160 * will time out, returning 0.
161 */
162 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
163 if (slow_clk == SLOW_CLK_32K_XTAL) {
164 rtc_clk_32k_enable(true);
165 } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
166 rtc_clk_32k_enable_external();
167 }
168 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
169 if (SLOW_CLK_CAL_CYCLES > 0) {
170 cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
171 if (cal_val == 0) {
172 if (retry_32k_xtal-- > 0) {
173 continue;
174 }
175 ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 90 kHz oscillator");
176 rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
177 }
178 }
179 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
180 rtc_clk_8m_enable(true, true);
181 }
182 rtc_clk_slow_src_set(rtc_slow_clk_src);
183
184 if (SLOW_CLK_CAL_CYCLES > 0) {
185 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
186 * Improve calibration routine to wait until the frequency is stable.
187 */
188 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
189 } else {
190 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
191 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
192 }
193 } while (cal_val == 0);
194 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
195 esp_clk_slowclk_cal_set(cal_val);
196 }
197
rtc_clk_select_rtc_slow_clk(void)198 void rtc_clk_select_rtc_slow_clk(void)
199 {
200 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
201 }
202
203 /* This function is not exposed as an API at this point.
204 * All peripheral clocks are default enabled after chip is powered on.
205 * This function disables some peripheral clocks when cpu starts.
206 * These peripheral clocks are enabled when the peripherals are initialized
207 * and disabled when they are de-initialized.
208 */
esp_perip_clk_init(void)209 __attribute__((weak)) void esp_perip_clk_init(void)
210 {
211 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
212 uint32_t common_perip_clk1 = 0;
213
214 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
215
216 /* For reason that only reset CPU, do not disable the clocks
217 * that have been enabled before reset.
218 */
219 if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
220 rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
221 common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
222 hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
223 wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
224 } else {
225 common_perip_clk = DPORT_WDG_CLK_EN |
226 DPORT_I2S0_CLK_EN |
227 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
228 DPORT_UART_CLK_EN |
229 #endif
230 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
231 DPORT_UART1_CLK_EN |
232 #endif
233 DPORT_SPI2_CLK_EN |
234 DPORT_I2C_EXT0_CLK_EN |
235 DPORT_UHCI0_CLK_EN |
236 DPORT_RMT_CLK_EN |
237 DPORT_PCNT_CLK_EN |
238 DPORT_LEDC_CLK_EN |
239 DPORT_TIMERGROUP1_CLK_EN |
240 DPORT_SPI3_CLK_EN |
241 DPORT_PWM0_CLK_EN |
242 DPORT_TWAI_CLK_EN |
243 DPORT_PWM1_CLK_EN |
244 DPORT_I2S1_CLK_EN |
245 DPORT_SPI2_DMA_CLK_EN |
246 DPORT_SPI3_DMA_CLK_EN |
247 DPORT_PWM2_CLK_EN |
248 DPORT_PWM3_CLK_EN;
249 common_perip_clk1 = 0;
250 hwcrypto_perip_clk = DPORT_CRYPTO_AES_CLK_EN |
251 DPORT_CRYPTO_SHA_CLK_EN |
252 DPORT_CRYPTO_RSA_CLK_EN;
253 wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
254 DPORT_WIFI_CLK_BT_EN_M |
255 DPORT_WIFI_CLK_UNUSED_BIT5 |
256 DPORT_WIFI_CLK_UNUSED_BIT12 |
257 DPORT_WIFI_CLK_SDIOSLAVE_EN |
258 DPORT_WIFI_CLK_SDIO_HOST_EN |
259 DPORT_WIFI_CLK_EMAC_EN;
260 }
261
262 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
263 common_perip_clk |= DPORT_I2S0_CLK_EN |
264 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
265 DPORT_UART_CLK_EN |
266 #endif
267 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
268 DPORT_UART1_CLK_EN |
269 #endif
270 #ifndef CONFIG_ESP32S2_KEEP_USB_ALIVE
271 DPORT_USB_CLK_EN |
272 #endif
273 DPORT_SPI2_CLK_EN |
274 DPORT_I2C_EXT0_CLK_EN |
275 DPORT_UHCI0_CLK_EN |
276 DPORT_RMT_CLK_EN |
277 DPORT_UHCI1_CLK_EN |
278 DPORT_SPI3_CLK_EN |
279 DPORT_I2C_EXT1_CLK_EN |
280 DPORT_I2S1_CLK_EN |
281 DPORT_SPI2_DMA_CLK_EN |
282 DPORT_SPI3_DMA_CLK_EN;
283 common_perip_clk1 = 0;
284
285 #ifndef CONFIG_IDF_ENV_FPGA
286 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
287 * the current is not reduced when disable I2S clock.
288 */
289 REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
290 REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
291 #endif // CONFIG_IDF_ENV_FPGA
292
293 /* Disable some peripheral clocks. */
294 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
295 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
296
297 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, common_perip_clk1);
298 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1);
299
300 /* Disable hardware crypto clocks. */
301 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
302 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
303
304 /* Disable WiFi/BT/SDIO clocks. */
305 DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
306
307 /* Enable WiFi MAC and POWER clocks */
308 DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
309
310 /* Set WiFi light sleep clock source to RTC slow clock */
311 DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0);
312 DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL32K | DPORT_LPCLK_SEL_XTAL | DPORT_LPCLK_SEL_8M | DPORT_LPCLK_SEL_RTC_SLOW);
313 DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
314
315
316 /* Enable RNG clock. */
317 periph_module_enable(PERIPH_RNG_MODULE);
318
319 /* Enable TimerGroup 0 clock to ensure its reference counter will never
320 * be decremented to 0 during normal operation and preventing it from
321 * being disabled.
322 * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
323 * registers (Flashboot protection included) will be reenabled, and some
324 * seconds later, will trigger an unintended reset.
325 */
326 periph_module_enable(PERIPH_TIMG0_MODULE);
327 }
328
