1 /*
2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <string.h>
8 #include "sdkconfig.h"
9 #include "esp_system.h"
10 #include "esp_private/system_internal.h"
11 #include "esp_attr.h"
12 #include "esp_log.h"
13 #include "esp_rom_sys.h"
14 #include "riscv/rv_utils.h"
15 #include "riscv/interrupt.h"
16 #include "esp_rom_uart.h"
17 #include "soc/gpio_reg.h"
18 #include "esp_cpu.h"
19 #include "soc/rtc.h"
20 #include "esp_private/rtc_clk.h"
21 #include "soc/rtc_periph.h"
22 #include "soc/uart_reg.h"
23 #include "hal/wdt_hal.h"
24 #include "hal/spimem_flash_ll.h"
25 #include "esp_private/cache_err_int.h"
26 #include "esp_private/spi_flash_os.h"
27
28 #include "esp32h2/rom/cache.h"
29 #include "esp32h2/rom/rtc.h"
30 #include "soc/pcr_reg.h"
31
esp_system_reset_modules_on_exit(void)32 void IRAM_ATTR esp_system_reset_modules_on_exit(void)
33 {
34 // Flush any data left in UART FIFOs before reset the UART peripheral
35 esp_rom_uart_tx_wait_idle(0);
36 esp_rom_uart_tx_wait_idle(1);
37
38 // Set Peripheral clk rst
39 SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
40 SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
41 SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
42 SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
43 SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
44 SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
45 SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
46
47 // Clear Peripheral clk rst
48 CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
49 CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
50 CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
51 CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
52 CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
53 CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
54 CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
55 }
56
57 /* "inner" restart function for after RTOS, interrupts & anything else on this
58 * core are already stopped. Stalls other core, resets hardware,
59 * triggers restart.
60 */
esp_restart_noos(void)61 void IRAM_ATTR esp_restart_noos(void)
62 {
63 // Disable interrupts
64 rv_utils_intr_global_disable();
65 // Enable RTC watchdog for 1 second
66 wdt_hal_context_t rtc_wdt_ctx;
67 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
68 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
69 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
70 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
71 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
72 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
73 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
74 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
75
76 // Disable TG0/TG1 watchdogs
77 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
78 wdt_hal_write_protect_disable(&wdt0_context);
79 wdt_hal_disable(&wdt0_context);
80 wdt_hal_write_protect_enable(&wdt0_context);
81
82 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
83 wdt_hal_write_protect_disable(&wdt1_context);
84 wdt_hal_disable(&wdt1_context);
85 wdt_hal_write_protect_enable(&wdt1_context);
86
87 // Disable cache
88 Cache_Disable_ICache();
89
90 // 2nd stage bootloader reconfigures SPI flash signals.
91 // Reset them to the defaults expected by ROM.
92 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
93
94 esp_system_reset_modules_on_exit();
95
96 // If we set mspi clock frequency to PLL, but ROM does not have such clock source option. So reset the clock to XTAL when software restart.
97 spi_flash_set_clock_src(MSPI_CLK_SRC_ROM_DEFAULT);
98
99 // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
100 #if !CONFIG_IDF_ENV_FPGA
101 rtc_clk_cpu_set_to_default_config();
102 #endif
103
104 // Reset CPU
105 esp_rom_software_reset_cpu(0);
106
107 while (true) {
108 ;
109 }
110 }
111
