1 /*
2 * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <sys/cdefs.h>
9 #include <sys/time.h>
10 #include <sys/param.h>
11 #include "sdkconfig.h"
12 #include "esp_attr.h"
13 #include "esp_log.h"
14 #include "esp_cpu.h"
15 #include "esp_clk_internal.h"
16 #include "esp32h2/rom/ets_sys.h"
17 #include "esp32h2/rom/uart.h"
18 #include "soc/soc.h"
19 #include "soc/rtc.h"
20 #include "soc/rtc_periph.h"
21 #include "soc/i2s_reg.h"
22 #include "soc/pcr_reg.h"
23 #include "hal/wdt_hal.h"
24 #include "esp_private/esp_modem_clock.h"
25 #include "esp_private/periph_ctrl.h"
26 #include "esp_private/esp_clk.h"
27 #include "esp_private/esp_pmu.h"
28 #include "esp_rom_uart.h"
29 #include "esp_rom_sys.h"
30 #include "esp_sleep.h"
31
32 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
33 * Larger values increase startup delay. Smaller values may cause false positive
34 * detection (i.e. oscillator runs for a few cycles and then stops).
35 */
36 #define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
37
38 #define MHZ (1000000)
39
40 static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
41 static __attribute__((unused)) void recalib_bbpll(void);
42
43 static const char *TAG = "clk";
44
45
esp_rtc_init(void)46 void esp_rtc_init(void)
47 {
48 #if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
49 // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
50 // Do calibration again here so that we can use better clock for the timing tuning.
51 recalib_bbpll();
52 #endif
53
54 #if !CONFIG_IDF_ENV_FPGA
55 pmu_init();
56 #endif
57 }
58
esp_clk_init(void)59 __attribute__((weak)) void esp_clk_init(void)
60 {
61 #if !CONFIG_IDF_ENV_FPGA
62 assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M);
63
64 rtc_clk_8m_enable(true);
65 rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
66 #endif
67
68 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
69 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
70 // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
71 // Therefore, for the time of frequency change, set a new lower timeout value (2 sec).
72 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
73 // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 2 sec * 150/32 = 9.375 sec).
74
75 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
76
77 uint32_t stage_timeout_ticks = (uint32_t)(2000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
78 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
79 wdt_hal_feed(&rtc_wdt_ctx);
80 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
81 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
82 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
83 #endif
84
85 modem_clock_deselect_all_module_lp_clock_source();
86 #if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
87 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
88 #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
89 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
90 #else
91 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
92 #endif
93
94 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
95 // After changing a frequency WDT timeout needs to be set for new frequency.
96 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
97 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
98 wdt_hal_feed(&rtc_wdt_ctx);
99 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
100 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
101 #endif
102
103 rtc_cpu_freq_config_t old_config, new_config;
104 rtc_clk_cpu_freq_get_config(&old_config);
105 const uint32_t old_freq_mhz = old_config.freq_mhz;
106 const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
107
108 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
109 assert(res);
110
111 // Wait for UART TX to finish, otherwise some UART output will be lost
112 // when switching APB frequency
113 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
114
115 if (res) {
116 rtc_clk_cpu_freq_set_config(&new_config);
117 }
118
119 // Re calculate the ccount to make time calculation correct.
120 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
121
122 // Set crypto clock (`clk_sec`) to use 96M PLL clock
123 REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3);
124 }
125
select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)126 static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
127 {
128 uint32_t cal_val = 0;
129 /* number of times to repeat 32k XTAL calibration
130 * before giving up and switching to the internal RC
131 */
132 int retry_32k_xtal = 3;
133
134 do {
135 if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K || rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
136 /* 32k XTAL oscillator needs to be enabled and running before it can
137 * be used. Hardware doesn't have a direct way of checking if the
138 * oscillator is running. Here we use rtc_clk_cal function to count
139 * the number of main XTAL cycles in the given number of 32k XTAL
140 * oscillator cycles. If the 32k XTAL has not started up, calibration
141 * will time out, returning 0.
142 */
143 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
144 rtc_cal_sel_t cal_sel = 0;
145 if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
146 rtc_clk_32k_enable(true);
147 cal_sel = RTC_CAL_32K_XTAL;
148 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
149 rtc_clk_32k_enable_external();
150 cal_sel = RTC_CAL_32K_OSC_SLOW;
151 }
152 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
153 if (SLOW_CLK_CAL_CYCLES > 0) {
154 cal_val = rtc_clk_cal(cal_sel, SLOW_CLK_CAL_CYCLES);
155 if (cal_val == 0) {
156 if (retry_32k_xtal-- > 0) {
157 continue;
158 }
159 ESP_EARLY_LOGW(TAG, "32 kHz clock not found, switching to internal 150 kHz oscillator");
160 rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
161 }
162 }
163 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
164 rtc_clk_rc32k_enable(true);
165 }
166 rtc_clk_slow_src_set(rtc_slow_clk_src);
167
168 // Disable unused clock sources after clock source switching is complete.
169 // Regardless of the clock source selection, the internal 136K clock source will always keep on.
170 if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
171 rtc_clk_32k_enable(false);
172 }
173 if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
174 rtc_clk_rc32k_enable(false);
175 }
176
177 if (SLOW_CLK_CAL_CYCLES > 0) {
178 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
179 * Improve calibration routine to wait until the frequency is stable.
180 */
181 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
182 } else {
183 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
184 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
185 }
186 } while (cal_val == 0);
187 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
188 esp_clk_slowclk_cal_set(cal_val);
189 }
190
rtc_clk_select_rtc_slow_clk(void)191 void rtc_clk_select_rtc_slow_clk(void)
192 {
193 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
194 }
195
196 /* This function is not exposed as an API at this point.
197 * All peripheral clocks are default enabled after chip is powered on.
198 * This function disables some peripheral clocks when cpu starts.
199 * These peripheral clocks are enabled when the peripherals are initialized
200 * and disabled when they are de-initialized.
201 */
esp_perip_clk_init(void)202 __attribute__((weak)) void esp_perip_clk_init(void)
203 {
204 soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
205 esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t) (\
206 (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \
207 : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \
208 : ESP_PD_DOMAIN_MAX);
209 esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON);
210
211 ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
212 // ESP32H2-TODO: IDF-5658
213 #if 0
214 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
215 uint32_t common_perip_clk1 = 0;
216
217 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
218
219 /* For reason that only reset CPU, do not disable the clocks
220 * that have been enabled before reset.
221 */
222 if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
223 rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
224 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
225 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
226 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
227 } else {
228 common_perip_clk = SYSTEM_WDG_CLK_EN |
229 SYSTEM_I2S0_CLK_EN |
230 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
231 SYSTEM_UART_CLK_EN |
232 #endif
233 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
234 SYSTEM_UART1_CLK_EN |
235 #endif
236 SYSTEM_SPI2_CLK_EN |
237 SYSTEM_I2C_EXT0_CLK_EN |
238 SYSTEM_UHCI0_CLK_EN |
239 SYSTEM_RMT_CLK_EN |
240 SYSTEM_LEDC_CLK_EN |
241 SYSTEM_TIMERGROUP1_CLK_EN |
242 SYSTEM_SPI3_CLK_EN |
243 SYSTEM_SPI4_CLK_EN |
244 SYSTEM_TWAI_CLK_EN |
245 SYSTEM_I2S1_CLK_EN |
246 SYSTEM_SPI2_DMA_CLK_EN |
247 SYSTEM_SPI3_DMA_CLK_EN;
248
249 common_perip_clk1 = 0;
250 hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
251 SYSTEM_CRYPTO_SHA_CLK_EN |
252 SYSTEM_CRYPTO_RSA_CLK_EN;
253 wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
254 SYSTEM_WIFI_CLK_BT_EN_M |
255 SYSTEM_WIFI_CLK_UNUSED_BIT5 |
256 SYSTEM_WIFI_CLK_UNUSED_BIT12;
257 }
258
259 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
260 common_perip_clk |= SYSTEM_I2S0_CLK_EN |
261 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
262 SYSTEM_UART_CLK_EN |
263 #endif
264 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
265 SYSTEM_UART1_CLK_EN |
266 #endif
267 SYSTEM_SPI2_CLK_EN |
268 SYSTEM_I2C_EXT0_CLK_EN |
269 SYSTEM_UHCI0_CLK_EN |
270 SYSTEM_RMT_CLK_EN |
271 SYSTEM_UHCI1_CLK_EN |
272 SYSTEM_SPI3_CLK_EN |
273 SYSTEM_SPI4_CLK_EN |
274 SYSTEM_I2C_EXT1_CLK_EN |
275 SYSTEM_I2S1_CLK_EN |
276 SYSTEM_SPI2_DMA_CLK_EN |
277 SYSTEM_SPI3_DMA_CLK_EN;
278 common_perip_clk1 = 0;
279
280 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
281 * the current is not reduced when disable I2S clock.
282 */
283 // TOCK(check replacement)
284 // REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
285 // REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
286
287 /* Disable some peripheral clocks. */
288 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
289 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
290
291 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
292 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
293
294 /* Disable hardware crypto clocks. */
295 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
296 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
297
298 /* Disable WiFi/BT/SDIO clocks. */
299 CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
300 SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
301
302 /* Set WiFi light sleep clock source to RTC slow clock */
303 REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
304 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
305 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
306
307 /* Enable RNG clock. */
308 periph_module_enable(PERIPH_RNG_MODULE);
309 #endif
310
311 /* Enable TimerGroup 0 clock to ensure its reference counter will never
312 * be decremented to 0 during normal operation and preventing it from
313 * being disabled.
314 * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
315 * registers (Flashboot protection included) will be reenabled, and some
316 * seconds later, will trigger an unintended reset.
317 */
318 periph_module_enable(PERIPH_TIMG0_MODULE);
319 }
320
321 // Workaround for bootloader not calibrated well issue.
322 // Placed in IRAM because disabling BBPLL may influence the cache
recalib_bbpll(void)323 static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
324 {
325 rtc_cpu_freq_config_t old_config;
326 rtc_clk_cpu_freq_get_config(&old_config);
327
328 // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
329 // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
330 // Turn off the BBPLL and do calibration again to fix the issue. Flash_PLL comes from the same source as PLL.
331 // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
332 // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
333 if (old_config.source == SOC_CPU_CLK_SRC_PLL || old_config.source == SOC_CPU_CLK_SRC_FLASH_PLL) {
334 rtc_clk_cpu_freq_set_xtal();
335 rtc_clk_cpu_freq_set_config(&old_config);
336 }
337 }
338
