1 /*
2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <string.h>
8 #include "sdkconfig.h"
9 #include "esp_system.h"
10 #include "esp_private/system_internal.h"
11 #include "esp_attr.h"
12 #include "esp_log.h"
13 #include "esp_rom_sys.h"
14 #include "riscv/rv_utils.h"
15 #include "esp_rom_uart.h"
16 #include "soc/gpio_reg.h"
17 #include "esp_cpu.h"
18 #include "soc/rtc.h"
19 #include "esp_private/rtc_clk.h"
20 #include "soc/rtc_periph.h"
21 #include "soc/uart_reg.h"
22 #include "hal/wdt_hal.h"
23 #include "hal/modem_syscon_ll.h"
24 #include "hal/modem_lpcon_ll.h"
25 #include "cache_err_int.h"
26
27 #include "esp32c6/rom/cache.h"
28 #include "esp32c6/rom/rtc.h"
29 #include "soc/pcr_reg.h"
30
esp_system_reset_modules_on_exit(void)31 void IRAM_ATTR esp_system_reset_modules_on_exit(void)
32 {
33 // Flush any data left in UART FIFOs before reset the UART peripheral
34 esp_rom_uart_tx_wait_idle(0);
35 esp_rom_uart_tx_wait_idle(1);
36
37 modem_syscon_ll_reset_all(&MODEM_SYSCON);
38 modem_lpcon_ll_reset_all(&MODEM_LPCON);
39
40 // Set Peripheral clk rst
41 SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
42 SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
43 SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
44 SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
45 SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
46 SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
47 SET_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN);
48 SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
49
50 // Clear Peripheral clk rst
51 CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
52 CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
53 CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
54 CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
55 CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
56 CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
57 CLEAR_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN);
58 CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
59 }
60
61 /* "inner" restart function for after RTOS, interrupts & anything else on this
62 * core are already stopped. Stalls other core, resets hardware,
63 * triggers restart.
64 */
esp_restart_noos(void)65 void IRAM_ATTR esp_restart_noos(void)
66 {
67 // Disable interrupts
68 rv_utils_intr_global_disable();
69 // Enable RTC watchdog for 1 second
70 wdt_hal_context_t rtc_wdt_ctx;
71 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
72 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
73 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
74 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
75 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
76 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
77 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
78 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
79
80 // C6 is a single core SoC, no need to reset and stall the other CPU
81
82 // Disable TG0/TG1 watchdogs
83 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
84 wdt_hal_write_protect_disable(&wdt0_context);
85 wdt_hal_disable(&wdt0_context);
86 wdt_hal_write_protect_enable(&wdt0_context);
87
88 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
89 wdt_hal_write_protect_disable(&wdt1_context);
90 wdt_hal_disable(&wdt1_context);
91 wdt_hal_write_protect_enable(&wdt1_context);
92
93 // Disable cache
94 Cache_Disable_ICache();
95
96 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
97 // Moved to module internal
98 // SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
99 // SYSTEM_SDIO_RST | // SDIO_HINF_HINF_SDIO_RST?
100 // SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | // TODO: IDF-5325 (ethernet)
101 // REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
102
103 esp_system_reset_modules_on_exit();
104
105 // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
106 #if !CONFIG_IDF_ENV_FPGA
107 rtc_clk_cpu_set_to_default_config();
108 #endif
109
110 // Reset PRO CPU
111 esp_rom_software_reset_cpu(0);
112 while (true) {
113 ;
114 }
115 }
116
