1 /*
2  * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include "esp_system.h"
8 #include "esp_rom_sys.h"
9 #include "esp_private/system_internal.h"
10 #include "soc/rtc_periph.h"
11 #include "esp32c6/rom/rtc.h"
12 
13 static void esp_reset_reason_clear_hint(void);
14 
15 static esp_reset_reason_t s_reset_reason;
16 
get_reset_reason(soc_reset_reason_t rtc_reset_reason,esp_reset_reason_t reset_reason_hint)17 static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
18 {
19     switch (rtc_reset_reason) {
20     case RESET_REASON_CHIP_POWER_ON:
21         return ESP_RST_POWERON;
22 
23     case RESET_REASON_CPU0_SW:
24     case RESET_REASON_CORE_SW:
25         if (reset_reason_hint == ESP_RST_PANIC ||
26             reset_reason_hint == ESP_RST_BROWNOUT ||
27             reset_reason_hint == ESP_RST_TASK_WDT ||
28             reset_reason_hint == ESP_RST_INT_WDT) {
29             return reset_reason_hint;
30         }
31         return ESP_RST_SW;
32 
33     case RESET_REASON_CORE_DEEP_SLEEP:
34         return ESP_RST_DEEPSLEEP;
35 
36     case RESET_REASON_CORE_MWDT0:
37         return ESP_RST_TASK_WDT;
38 
39     case RESET_REASON_CORE_MWDT1:
40         return ESP_RST_INT_WDT;
41 
42     case RESET_REASON_CORE_RTC_WDT:
43     case RESET_REASON_SYS_RTC_WDT:
44     case RESET_REASON_SYS_SUPER_WDT:
45     case RESET_REASON_CPU0_RTC_WDT:
46     case RESET_REASON_CPU0_MWDT0:
47     case RESET_REASON_CPU0_MWDT1:
48         return ESP_RST_WDT;
49 
50     case RESET_REASON_SYS_BROWN_OUT:
51         return ESP_RST_BROWNOUT;
52 
53     case RESET_REASON_CORE_USB_UART:
54     case RESET_REASON_CORE_USB_JTAG:
55         return ESP_RST_USB;
56 
57     case RESET_REASON_CORE_EFUSE_CRC:
58         return ESP_RST_EFUSE;
59 
60     case RESET_REASON_CPU0_JTAG:
61         return ESP_RST_JTAG;
62 
63     case RESET_REASON_CORE_SDIO:
64         return ESP_RST_SDIO;
65 
66     default:
67         return ESP_RST_UNKNOWN;
68     }
69 }
70 
esp_reset_reason_init(void)71 void esp_reset_reason_init(void)
72 {
73     esp_reset_reason_t hint = esp_reset_reason_get_hint();
74     s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
75     if (hint != ESP_RST_UNKNOWN) {
76         esp_reset_reason_clear_hint();
77     }
78 }
79 
esp_reset_reason(void)80 esp_reset_reason_t esp_reset_reason(void)
81 {
82     return s_reset_reason;
83 }
84 
85 /* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG,
86  * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
87  * deep sleep wake stub entry address and for reset reason hint, since wake stub
88  * is only used for deep sleep reset, and in this case the reason provided by
89  * esp_rom_get_reset_reason is unambiguous.
90  *
91  * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
92  * the value is replicated in low and high half-words. In addition to that,
93  * MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains
94  * deep sleep wake stub address.
95  */
96 
97 #define RST_REASON_BIT  0x80000000
98 #define RST_REASON_MASK 0x7FFF
99 #define RST_REASON_SHIFT 16
100 
101 /* in IRAM, can be called from panic handler */
esp_reset_reason_set_hint(esp_reset_reason_t hint)102 void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
103 {
104     assert((hint & (~RST_REASON_MASK)) == 0);
105     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
106     REG_WRITE(RTC_RESET_CAUSE_REG, val);
107 }
108 
109 /* in IRAM, can be called from panic handler */
esp_reset_reason_get_hint(void)110 esp_reset_reason_t esp_reset_reason_get_hint(void)
111 {
112     uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
113     uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;
114     uint32_t low = reset_reason_hint & RST_REASON_MASK;
115     if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) {
116         return ESP_RST_UNKNOWN;
117     }
118     return (esp_reset_reason_t) low;
119 }
esp_reset_reason_clear_hint(void)120 static inline void esp_reset_reason_clear_hint(void)
121 {
122     REG_WRITE(RTC_RESET_CAUSE_REG, 0);
123 }
124