1 /*
2 * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <sys/cdefs.h>
9 #include <sys/param.h>
10 #include "sdkconfig.h"
11 #include "esp_attr.h"
12 #include "esp_log.h"
13 #include "esp_clk_internal.h"
14 #include "esp32c6/rom/ets_sys.h"
15 #include "esp32c6/rom/uart.h"
16 #include "soc/soc.h"
17 #include "soc/rtc.h"
18 #include "soc/rtc_periph.h"
19 #include "soc/i2s_reg.h"
20 #include "esp_cpu.h"
21 #include "hal/wdt_hal.h"
22 #include "esp_private/esp_modem_clock.h"
23 #include "esp_private/periph_ctrl.h"
24 #include "esp_private/esp_clk.h"
25 #include "esp_private/esp_pmu.h"
26 #include "esp_rom_uart.h"
27 #include "esp_rom_sys.h"
28 #include "ocode_init.h"
29
30 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
31 * Larger values increase startup delay. Smaller values may cause false positive
32 * detection (i.e. oscillator runs for a few cycles and then stops).
33 */
34 #define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
35
36 static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
37 static __attribute__((unused)) void recalib_bbpll(void);
38
39 static const char *TAG = "clk";
40
41
esp_rtc_init(void)42 void esp_rtc_init(void)
43 {
44 #if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
45 // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
46 // Do calibration again here so that we can use better clock for the timing tuning.
47 recalib_bbpll();
48 #endif
49
50 #if !CONFIG_IDF_ENV_FPGA
51 pmu_init();
52 if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) {
53 esp_ocode_calib_init();
54 }
55 #endif
56 }
57
esp_clk_init(void)58 __attribute__((weak)) void esp_clk_init(void)
59 {
60 #if !CONFIG_IDF_ENV_FPGA
61 assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
62
63 rtc_clk_8m_enable(true);
64 rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
65 #endif
66
67 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
68 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
69 // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
70 // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
71 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
72 // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
73 wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
74 uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
75 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
76 wdt_hal_feed(&rtc_wdt_ctx);
77 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
78 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
79 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
80 #endif
81
82 modem_clock_deselect_all_module_lp_clock_source();
83 #if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
84 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
85 #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
86 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
87 #elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K)
88 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC32K);
89 #else
90 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
91 #endif
92
93 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
94 // After changing a frequency WDT timeout needs to be set for new frequency.
95 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
96 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
97 wdt_hal_feed(&rtc_wdt_ctx);
98 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
99 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
100 #endif
101
102 rtc_cpu_freq_config_t old_config, new_config;
103 rtc_clk_cpu_freq_get_config(&old_config);
104 const uint32_t old_freq_mhz = old_config.freq_mhz;
105 const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
106
107 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
108 assert(res);
109
110 // Wait for UART TX to finish, otherwise some UART output will be lost
111 // when switching APB frequency
112 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
113
114 if (res) {
115 rtc_clk_cpu_freq_set_config(&new_config);
116 }
117
118 // Re calculate the ccount to make time calculation correct.
119 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
120 }
121
select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)122 static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
123 {
124 uint32_t cal_val = 0;
125 /* number of times to repeat 32k XTAL calibration
126 * before giving up and switching to the internal RC
127 */
128 int retry_32k_xtal = 3;
129
130 do {
131 if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K || rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
132 /* 32k XTAL oscillator needs to be enabled and running before it can
133 * be used. Hardware doesn't have a direct way of checking if the
134 * oscillator is running. Here we use rtc_clk_cal function to count
135 * the number of main XTAL cycles in the given number of 32k XTAL
136 * oscillator cycles. If the 32k XTAL has not started up, calibration
137 * will time out, returning 0.
138 */
139 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
140 rtc_cal_sel_t cal_sel = 0;
141 if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
142 rtc_clk_32k_enable(true);
143 cal_sel = RTC_CAL_32K_XTAL;
144 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
145 rtc_clk_32k_enable_external();
146 cal_sel = RTC_CAL_32K_OSC_SLOW;
147 }
148 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
149 if (SLOW_CLK_CAL_CYCLES > 0) {
150 cal_val = rtc_clk_cal(cal_sel, SLOW_CLK_CAL_CYCLES);
151 if (cal_val == 0) {
152 if (retry_32k_xtal-- > 0) {
153 continue;
154 }
155 ESP_EARLY_LOGW(TAG, "32 kHz clock not found, switching to internal 150 kHz oscillator");
156 rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
157 }
158 }
159 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
160 rtc_clk_rc32k_enable(true);
161 }
162 rtc_clk_slow_src_set(rtc_slow_clk_src);
163
164 // Disable unused clock sources after clock source switching is complete.
165 // Regardless of the clock source selection, the internal 136K clock source will always keep on.
166 if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
167 rtc_clk_32k_enable(false);
168 }
169 if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
170 rtc_clk_rc32k_enable(false);
171 }
172
173 if (SLOW_CLK_CAL_CYCLES > 0) {
174 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
175 * Improve calibration routine to wait until the frequency is stable.
176 */
177 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
178 } else {
179 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
180 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
181 }
182 } while (cal_val == 0);
183 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
184 esp_clk_slowclk_cal_set(cal_val);
185 }
186
rtc_clk_select_rtc_slow_clk(void)187 void rtc_clk_select_rtc_slow_clk(void)
188 {
189 select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
190 }
191
192 /* This function is not exposed as an API at this point.
193 * All peripheral clocks are default enabled after chip is powered on.
194 * This function disables some peripheral clocks when cpu starts.
195 * These peripheral clocks are enabled when the peripherals are initialized
196 * and disabled when they are de-initialized.
197 */
esp_perip_clk_init(void)198 __attribute__((weak)) void esp_perip_clk_init(void)
199 {
200 /* During system initialization, the low-power clock source of the modem
201 * (WiFi, BLE or Coexist) follows the configuration of the slow clock source
202 * of the system. If the WiFi, BLE or Coexist module needs a higher
203 * precision sleep clock (for example, the BLE needs to use the main XTAL
204 * oscillator (40 MHz) to provide the clock during the sleep process in some
205 * scenarios), the module needs to switch to the required clock source by
206 * itself. */ //TODO - WIFI-5233
207 soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
208 modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t) ( \
209 (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW \
210 : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
211 : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
212 : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
213 : SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
214 modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
215
216 ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
217 #if 0 // TODO: IDF-5658
218 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
219 uint32_t common_perip_clk1 = 0;
220
221 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
222
223 /* For reason that only reset CPU, do not disable the clocks
224 * that have been enabled before reset.
225 */
226 if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
227 rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
228 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
229 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
230 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
231 } else {
232 common_perip_clk = SYSTEM_WDG_CLK_EN |
233 SYSTEM_I2S0_CLK_EN |
234 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
235 SYSTEM_UART_CLK_EN |
236 #endif
237 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
238 SYSTEM_UART1_CLK_EN |
239 #endif
240 SYSTEM_SPI2_CLK_EN |
241 SYSTEM_I2C_EXT0_CLK_EN |
242 SYSTEM_UHCI0_CLK_EN |
243 SYSTEM_RMT_CLK_EN |
244 SYSTEM_LEDC_CLK_EN |
245 SYSTEM_TIMERGROUP1_CLK_EN |
246 SYSTEM_SPI3_CLK_EN |
247 SYSTEM_SPI4_CLK_EN |
248 SYSTEM_TWAI_CLK_EN |
249 SYSTEM_I2S1_CLK_EN |
250 SYSTEM_SPI2_DMA_CLK_EN |
251 SYSTEM_SPI3_DMA_CLK_EN;
252
253 common_perip_clk1 = 0;
254 hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
255 SYSTEM_CRYPTO_SHA_CLK_EN |
256 SYSTEM_CRYPTO_RSA_CLK_EN;
257 wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
258 SYSTEM_WIFI_CLK_BT_EN_M |
259 SYSTEM_WIFI_CLK_UNUSED_BIT5 |
260 SYSTEM_WIFI_CLK_UNUSED_BIT12;
261 }
262
263 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
264 common_perip_clk |= SYSTEM_I2S0_CLK_EN |
265 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
266 SYSTEM_UART_CLK_EN |
267 #endif
268 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
269 SYSTEM_UART1_CLK_EN |
270 #endif
271 SYSTEM_SPI2_CLK_EN |
272 SYSTEM_I2C_EXT0_CLK_EN |
273 SYSTEM_UHCI0_CLK_EN |
274 SYSTEM_RMT_CLK_EN |
275 SYSTEM_UHCI1_CLK_EN |
276 SYSTEM_SPI3_CLK_EN |
277 SYSTEM_SPI4_CLK_EN |
278 SYSTEM_I2C_EXT1_CLK_EN |
279 SYSTEM_I2S1_CLK_EN |
280 SYSTEM_SPI2_DMA_CLK_EN |
281 SYSTEM_SPI3_DMA_CLK_EN;
282 common_perip_clk1 = 0;
283
284 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
285 * the current is not reduced when disable I2S clock.
286 */
287 // TOCK(check replacement)
288 // REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
289 // REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
290
291 /* Disable some peripheral clocks. */
292 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
293 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
294
295 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
296 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
297
298 /* Disable hardware crypto clocks. */
299 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
300 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
301
302 /* Disable WiFi/BT/SDIO clocks. */
303 CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
304 SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
305
306 /* Set WiFi light sleep clock source to RTC slow clock */
307 REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
308 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
309 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
310
311 /* Enable RNG clock. */
312 periph_module_enable(PERIPH_RNG_MODULE);
313 #endif
314
315 /* Enable TimerGroup 0 clock to ensure its reference counter will never
316 * be decremented to 0 during normal operation and preventing it from
317 * being disabled.
318 * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
319 * registers (Flashboot protection included) will be reenabled, and some
320 * seconds later, will trigger an unintended reset.
321 */
322 periph_module_enable(PERIPH_TIMG0_MODULE);
323 }
324
325 // Workaround for bootloader not calibrated well issue.
326 // Placed in IRAM because disabling BBPLL may influence the cache
recalib_bbpll(void)327 static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
328 {
329 rtc_cpu_freq_config_t old_config;
330 rtc_clk_cpu_freq_get_config(&old_config);
331
332 // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
333 // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
334 // Turn off the BBPLL and do calibration again to fix the issue.
335 // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
336 // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
337 if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
338 rtc_clk_cpu_freq_set_xtal();
339 rtc_clk_cpu_freq_set_config(&old_config);
340 }
341 }
342
