1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "esp_system.h"
8 #include "esp_rom_sys.h"
9 #include "esp_private/system_internal.h"
10 #include "soc/rtc_periph.h"
11 #include "esp32c3/rom/rtc.h"
12
13 static void esp_reset_reason_clear_hint(void);
14
15 static esp_reset_reason_t s_reset_reason;
16
get_reset_reason(soc_reset_reason_t rtc_reset_reason,esp_reset_reason_t reset_reason_hint)17 static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
18 {
19 switch (rtc_reset_reason) {
20 case RESET_REASON_CHIP_POWER_ON:
21 #if SOC_EFUSE_HAS_EFUSE_RST_BUG
22 case RESET_REASON_CORE_EFUSE_CRC:
23 #endif
24 return ESP_RST_POWERON;
25
26 case RESET_REASON_CPU0_SW:
27 case RESET_REASON_CORE_SW:
28 if (reset_reason_hint == ESP_RST_PANIC ||
29 reset_reason_hint == ESP_RST_BROWNOUT ||
30 reset_reason_hint == ESP_RST_TASK_WDT ||
31 reset_reason_hint == ESP_RST_INT_WDT) {
32 return reset_reason_hint;
33 }
34 return ESP_RST_SW;
35
36 case RESET_REASON_CORE_DEEP_SLEEP:
37 return ESP_RST_DEEPSLEEP;
38
39 case RESET_REASON_CORE_MWDT0:
40 return ESP_RST_TASK_WDT;
41
42 case RESET_REASON_CORE_MWDT1:
43 return ESP_RST_INT_WDT;
44
45 case RESET_REASON_CORE_RTC_WDT:
46 case RESET_REASON_SYS_RTC_WDT:
47 case RESET_REASON_SYS_SUPER_WDT:
48 case RESET_REASON_CPU0_RTC_WDT:
49 case RESET_REASON_CPU0_MWDT0:
50 case RESET_REASON_CPU0_MWDT1:
51 return ESP_RST_WDT;
52
53 case RESET_REASON_SYS_BROWN_OUT:
54 return ESP_RST_BROWNOUT;
55
56 default:
57 return ESP_RST_UNKNOWN;
58 }
59 }
60
esp_reset_reason_init(void)61 void esp_reset_reason_init(void)
62 {
63 esp_reset_reason_t hint = esp_reset_reason_get_hint();
64 s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
65 if (hint != ESP_RST_UNKNOWN) {
66 esp_reset_reason_clear_hint();
67 }
68 }
69
esp_reset_reason(void)70 esp_reset_reason_t esp_reset_reason(void)
71 {
72 return s_reset_reason;
73 }
74
75 /* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG,
76 * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
77 * deep sleep wake stub entry address and for reset reason hint, since wake stub
78 * is only used for deep sleep reset, and in this case the reason provided by
79 * esp_rom_get_reset_reason is unambiguous.
80 *
81 * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
82 * the value is replicated in low and high half-words. In addition to that,
83 * MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains
84 * deep sleep wake stub address.
85 */
86
87 #define RST_REASON_BIT 0x80000000
88 #define RST_REASON_MASK 0x7FFF
89 #define RST_REASON_SHIFT 16
90
91 /* in IRAM, can be called from panic handler */
esp_reset_reason_set_hint(esp_reset_reason_t hint)92 void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
93 {
94 assert((hint & (~RST_REASON_MASK)) == 0);
95 uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
96 REG_WRITE(RTC_RESET_CAUSE_REG, val);
97 }
98
99 /* in IRAM, can be called from panic handler */
esp_reset_reason_get_hint(void)100 esp_reset_reason_t esp_reset_reason_get_hint(void)
101 {
102 uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
103 uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;
104 uint32_t low = reset_reason_hint & RST_REASON_MASK;
105 if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) {
106 return ESP_RST_UNKNOWN;
107 }
108 return (esp_reset_reason_t) low;
109 }
esp_reset_reason_clear_hint(void)110 static inline void esp_reset_reason_clear_hint(void)
111 {
112 REG_WRITE(RTC_RESET_CAUSE_REG, 0);
113 }
114
