1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <sys/cdefs.h>
9 // #include <sys/time.h>
10 #include <sys/param.h>
11 #include "sdkconfig.h"
12 #include "esp_attr.h"
13 #include "esp_log.h"
14 #include "esp_cpu.h"
15 #include "esp_clk_internal.h"
16 #include "esp32c3/rom/ets_sys.h"
17 #include "esp32c3/rom/uart.h"
18 #include "soc/system_reg.h"
19 #include "soc/soc.h"
20 #include "soc/rtc.h"
21 #include "soc/rtc_periph.h"
22 #include "soc/i2s_reg.h"
23 #include "hal/wdt_hal.h"
24 #include "esp_private/periph_ctrl.h"
25 #include "esp_private/esp_clk.h"
26 #include "soc/syscon_reg.h"
27 #include "esp_rom_uart.h"
28 #include "esp_rom_sys.h"
29
30 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
31 * Larger values increase startup delay. Smaller values may cause false positive
32 * detection (i.e. oscillator runs for a few cycles and then stops).
33 */
34 #define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
35
36 /* Indicates that this 32k oscillator gets input from external oscillator, rather
37 * than a crystal.
38 */
39 #define EXT_OSC_FLAG BIT(3)
40
41 /* This is almost the same as soc_rtc_slow_clk_src_t, except that we define
42 * an extra enum member for the external 32k oscillator.
43 * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values.
44 */
45 typedef enum {
46 SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator
47 SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL
48 SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256
49 SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
50 } slow_clk_sel_t;
51
52 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
53
54 static const char *TAG = "clk";
55
56
esp_rtc_init(void)57 void esp_rtc_init(void)
58 {
59 #if !CONFIG_IDF_ENV_FPGA
60 rtc_config_t cfg = RTC_CONFIG_DEFAULT();
61 soc_reset_reason_t rst_reas;
62 rst_reas = esp_rom_get_reset_reason(0);
63 if (rst_reas == RESET_REASON_CHIP_POWER_ON
64 #if SOC_EFUSE_HAS_EFUSE_RST_BUG
65 || rst_reas == RESET_REASON_CORE_EFUSE_CRC
66 #endif
67 ) {
68 cfg.cali_ocode = 1;
69 }
70 rtc_init(cfg);
71 }
72
esp_clk_init(void)73 __attribute__((weak)) void esp_clk_init(void)
74 {
75 assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
76
77 bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
78 rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
79 rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
80 #endif
81
82 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
83 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
84 // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
85 // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
86 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
87 // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
88 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
89 uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
90 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
91 wdt_hal_feed(&rtc_wdt_ctx);
92 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
93 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
94 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
95 #endif
96
97 #if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
98 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
99 #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
100 select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
101 #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
102 select_rtc_slow_clk(SLOW_CLK_8MD256);
103 #else
104 select_rtc_slow_clk(SLOW_CLK_RTC);
105 #endif
106
107 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
108 // After changing a frequency WDT timeout needs to be set for new frequency.
109 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
110 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
111 wdt_hal_feed(&rtc_wdt_ctx);
112 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
113 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
114 #endif
115
116 rtc_cpu_freq_config_t old_config, new_config;
117 rtc_clk_cpu_freq_get_config(&old_config);
118 const uint32_t old_freq_mhz = old_config.freq_mhz;
119 const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
120
121 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
122 assert(res);
123
124 // Wait for UART TX to finish, otherwise some UART output will be lost
125 // when switching APB frequency
126 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
127
128 if (res) {
129 rtc_clk_cpu_freq_set_config(&new_config);
130 }
131
132 // Re calculate the ccount to make time calculation correct.
133 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
134 }
135
select_rtc_slow_clk(slow_clk_sel_t slow_clk)136 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
137 {
138 soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
139 uint32_t cal_val = 0;
140 /* number of times to repeat 32k XTAL calibration
141 * before giving up and switching to the internal RC
142 */
143 int retry_32k_xtal = 3;
144
145 do {
146 if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
147 /* 32k XTAL oscillator needs to be enabled and running before it can
148 * be used. Hardware doesn't have a direct way of checking if the
149 * oscillator is running. Here we use rtc_clk_cal function to count
150 * the number of main XTAL cycles in the given number of 32k XTAL
151 * oscillator cycles. If the 32k XTAL has not started up, calibration
152 * will time out, returning 0.
153 */
154 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
155 if (slow_clk == SLOW_CLK_32K_XTAL) {
156 rtc_clk_32k_enable(true);
157 } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
158 rtc_clk_32k_enable_external();
159 }
160 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
161 if (SLOW_CLK_CAL_CYCLES > 0) {
162 cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
163 if (cal_val == 0) {
164 if (retry_32k_xtal-- > 0) {
165 continue;
166 }
167 ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator");
168 rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
169 }
170 }
171 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
172 rtc_clk_8m_enable(true, true);
173 }
174 rtc_clk_slow_src_set(rtc_slow_clk_src);
175
176 if (SLOW_CLK_CAL_CYCLES > 0) {
177 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
178 * Improve calibration routine to wait until the frequency is stable.
179 */
180 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
181 } else {
182 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
183 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
184 }
185 } while (cal_val == 0);
186 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
187 esp_clk_slowclk_cal_set(cal_val);
188 }
189
rtc_clk_select_rtc_slow_clk(void)190 void rtc_clk_select_rtc_slow_clk(void)
191 {
192 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
193 }
194
195 /* This function is not exposed as an API at this point.
196 * All peripheral clocks are default enabled after chip is powered on.
197 * This function disables some peripheral clocks when cpu starts.
198 * These peripheral clocks are enabled when the peripherals are initialized
199 * and disabled when they are de-initialized.
200 */
esp_perip_clk_init(void)201 __attribute__((weak)) void esp_perip_clk_init(void)
202 {
203 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
204 uint32_t common_perip_clk1 = 0;
205
206 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
207
208 /* For reason that only reset CPU, do not disable the clocks
209 * that have been enabled before reset.
210 */
211 if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
212 rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
213 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
214 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
215 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
216 } else {
217 common_perip_clk = SYSTEM_WDG_CLK_EN |
218 SYSTEM_I2S0_CLK_EN |
219 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
220 SYSTEM_UART_CLK_EN |
221 #endif
222 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
223 SYSTEM_UART1_CLK_EN |
224 #endif
225 SYSTEM_SPI2_CLK_EN |
226 SYSTEM_I2C_EXT0_CLK_EN |
227 SYSTEM_UHCI0_CLK_EN |
228 SYSTEM_RMT_CLK_EN |
229 SYSTEM_LEDC_CLK_EN |
230 SYSTEM_TIMERGROUP1_CLK_EN |
231 SYSTEM_SPI3_CLK_EN |
232 SYSTEM_SPI4_CLK_EN |
233 SYSTEM_TWAI_CLK_EN |
234 SYSTEM_I2S1_CLK_EN |
235 SYSTEM_SPI2_DMA_CLK_EN |
236 SYSTEM_SPI3_DMA_CLK_EN;
237
238 common_perip_clk1 = 0;
239 hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
240 SYSTEM_CRYPTO_SHA_CLK_EN |
241 SYSTEM_CRYPTO_RSA_CLK_EN;
242 wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
243 SYSTEM_WIFI_CLK_BT_EN_M |
244 SYSTEM_WIFI_CLK_I2C_CLK_EN |
245 SYSTEM_WIFI_CLK_UNUSED_BIT12;
246 }
247
248 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
249 common_perip_clk |= SYSTEM_I2S0_CLK_EN |
250 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
251 SYSTEM_UART_CLK_EN |
252 #endif
253 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
254 SYSTEM_UART1_CLK_EN |
255 #endif
256 SYSTEM_SPI2_CLK_EN |
257 SYSTEM_I2C_EXT0_CLK_EN |
258 SYSTEM_UHCI0_CLK_EN |
259 SYSTEM_RMT_CLK_EN |
260 SYSTEM_UHCI1_CLK_EN |
261 SYSTEM_SPI3_CLK_EN |
262 SYSTEM_SPI4_CLK_EN |
263 SYSTEM_I2C_EXT1_CLK_EN |
264 SYSTEM_I2S1_CLK_EN |
265 SYSTEM_SPI2_DMA_CLK_EN |
266 SYSTEM_SPI3_DMA_CLK_EN;
267 common_perip_clk1 = 0;
268
269 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
270 * the current is not reduced when disable I2S clock.
271 */
272 // TOCK(check replacement)
273 // REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
274 // REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
275
276 /* Disable some peripheral clocks. */
277 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
278 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
279
280 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
281 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
282
283 /* Disable hardware crypto clocks. */
284 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
285 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
286
287 /* Disable WiFi/BT/SDIO clocks. */
288 CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
289 SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
290
291 /* Set WiFi light sleep clock source to RTC slow clock */
292 REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
293 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
294 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
295
296 /* Enable RNG clock. */
297 periph_module_enable(PERIPH_RNG_MODULE);
298
299 /* Enable TimerGroup 0 clock to ensure its reference counter will never
300 * be decremented to 0 during normal operation and preventing it from
301 * being disabled.
302 * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
303 * registers (Flashboot protection included) will be reenabled, and some
304 * seconds later, will trigger an unintended reset.
305 */
306 periph_module_enable(PERIPH_TIMG0_MODULE);
307 }
308
