1 /*
2  * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include "esp_system.h"
8 #include "esp_rom_sys.h"
9 #include "esp_private/system_internal.h"
10 #include "soc/rtc_periph.h"
11 #include "esp32/rom/rtc.h"
12 
13 static void esp_reset_reason_clear_hint(void);
14 
15 static esp_reset_reason_t s_reset_reason;
16 
get_reset_reason(uint32_t rtc_reset_reason,esp_reset_reason_t reset_reason_hint)17 static esp_reset_reason_t get_reset_reason(uint32_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
18 {
19     switch (rtc_reset_reason) {
20     case RESET_REASON_CHIP_POWER_ON:
21         return ESP_RST_POWERON;
22 
23     case RESET_REASON_CPU0_SW:
24     case RESET_REASON_CORE_SW:
25         if (reset_reason_hint == ESP_RST_PANIC ||
26                 reset_reason_hint == ESP_RST_BROWNOUT ||
27                 reset_reason_hint == ESP_RST_TASK_WDT ||
28                 reset_reason_hint == ESP_RST_INT_WDT) {
29             return reset_reason_hint;
30         }
31         return ESP_RST_SW;
32 
33     case RESET_REASON_CORE_DEEP_SLEEP:
34         return ESP_RST_DEEPSLEEP;
35 
36     case RESET_REASON_CORE_MWDT0:
37         return ESP_RST_TASK_WDT;
38 
39     case RESET_REASON_CORE_MWDT1:
40         return ESP_RST_INT_WDT;
41 
42     case RESET_REASON_CORE_RTC_WDT:
43     case RESET_REASON_SYS_RTC_WDT:
44     case RESET_REASON_CPU0_RTC_WDT:
45     case RESET_REASON_CPU0_MWDT0:
46         return ESP_RST_WDT;
47 
48     case RESET_REASON_SYS_BROWN_OUT:
49         return ESP_RST_BROWNOUT;
50 
51     case RESET_REASON_CORE_SDIO:
52         return ESP_RST_SDIO;
53 
54     default:
55         return ESP_RST_UNKNOWN;
56     }
57 }
58 
esp_reset_reason_init(void)59 void esp_reset_reason_init(void)
60 {
61     esp_reset_reason_t hint = esp_reset_reason_get_hint();
62     s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
63     if (hint != ESP_RST_UNKNOWN) {
64         esp_reset_reason_clear_hint();
65     }
66 }
67 
esp_reset_reason(void)68 esp_reset_reason_t esp_reset_reason(void)
69 {
70     return s_reset_reason;
71 }
72 
73 /* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG,
74  * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
75  * deep sleep wake stub entry address and for reset reason hint, since wake stub
76  * is only used for deep sleep reset, and in this case the reason provided by
77  * esp_rom_get_reset_reason is unambiguous.
78  *
79  * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
80  * the value is replicated in low and high half-words. In addition to that,
81  * MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains
82  * deep sleep wake stub address.
83  */
84 
85 #define RST_REASON_BIT  0x80000000
86 #define RST_REASON_MASK 0x7FFF
87 #define RST_REASON_SHIFT 16
88 
89 /* in IRAM, can be called from panic handler */
esp_reset_reason_set_hint(esp_reset_reason_t hint)90 void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
91 {
92     assert((hint & (~RST_REASON_MASK)) == 0);
93     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
94     REG_WRITE(RTC_RESET_CAUSE_REG, val);
95 }
96 
97 /* in IRAM, can be called from panic handler */
esp_reset_reason_get_hint(void)98 esp_reset_reason_t esp_reset_reason_get_hint(void)
99 {
100     uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
101     uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;
102     uint32_t low = reset_reason_hint & RST_REASON_MASK;
103     if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) {
104         return ESP_RST_UNKNOWN;
105     }
106     return (esp_reset_reason_t) low;
107 }
esp_reset_reason_clear_hint(void)108 static void esp_reset_reason_clear_hint(void)
109 {
110     REG_WRITE(RTC_RESET_CAUSE_REG, 0);
111 }
112