1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "soc/rtc.h"
8 #include "soc/dport_reg.h"
9 #include "soc/i2s_reg.h"
10 #include "esp_private/periph_ctrl.h"
11 #include "esp_private/esp_clk.h"
12 // #include "bootloader_clock.h"
13 #include "hal/wdt_hal.h"
14
15 // #include "esp_private/spi_common_internal.h" // [refactor-todo]: for spicommon_periph_in_use
16
17 #include "esp_log.h"
18 #include "esp_cpu.h"
19
20 #include "esp_rom_uart.h"
21 #include "esp_rom_sys.h"
22
23
24
25 static const char* TAG = "clk";
26
27 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
28 * Larger values increase startup delay. Smaller values may cause false positive
29 * detection (i.e. oscillator runs for a few cycles and then stops).
30 */
31 #define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
32
33 #ifdef CONFIG_RTC_XTAL_CAL_RETRY
34 #define RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RETRY
35 #else
36 #define RTC_XTAL_CAL_RETRY 1
37 #endif
38
39 /* Indicates that this 32k oscillator gets input from external oscillator, rather
40 * than a crystal.
41 */
42 #define EXT_OSC_FLAG BIT(3)
43
44 /* This is almost the same as soc_rtc_slow_clk_src_t, except that we define
45 * an extra enum member for the external 32k oscillator.
46 * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values.
47 */
48 typedef enum {
49 SLOW_CLK_150K = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator
50 SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL
51 SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256
52 SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
53 } slow_clk_sel_t;
54
select_rtc_slow_clk(slow_clk_sel_t slow_clk)55 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
56 {
57 soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
58 uint32_t cal_val = 0;
59 /* number of times to repeat 32k XTAL calibration
60 * before giving up and switching to the internal RC
61 */
62 int retry_32k_xtal = RTC_XTAL_CAL_RETRY;
63
64 do {
65 if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
66 /* 32k XTAL oscillator needs to be enabled and running before it can
67 * be used. Hardware doesn't have a direct way of checking if the
68 * oscillator is running. Here we use rtc_clk_cal function to count
69 * the number of main XTAL cycles in the given number of 32k XTAL
70 * oscillator cycles. If the 32k XTAL has not started up, calibration
71 * will time out, returning 0.
72 */
73 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
74 if (slow_clk == SLOW_CLK_32K_XTAL) {
75 rtc_clk_32k_enable(true);
76 } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
77 rtc_clk_32k_enable_external();
78 }
79 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
80 if (SLOW_CLK_CAL_CYCLES > 0) {
81 cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
82 if (cal_val == 0) {
83 if (retry_32k_xtal-- > 0) {
84 continue;
85 }
86 ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator");
87 rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
88 }
89 }
90 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
91 rtc_clk_8m_enable(true, true);
92 }
93 rtc_clk_slow_src_set(rtc_slow_clk_src);
94
95 if (SLOW_CLK_CAL_CYCLES > 0) {
96 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
97 * Improve calibration routine to wait until the frequency is stable.
98 */
99 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
100 } else {
101 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
102 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
103 }
104 } while (cal_val == 0);
105 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
106 esp_clk_slowclk_cal_set(cal_val);
107 }
108
esp_rtc_init(void)109 void esp_rtc_init(void)
110 {
111 rtc_config_t cfg = RTC_CONFIG_DEFAULT();
112 rtc_init(cfg);
113 }
114
esp_clk_init(void)115 __attribute__((weak)) void esp_clk_init(void)
116 {
117 #if (CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS || CONFIG_APP_INIT_CLK)
118 /* Check the bootloader set the XTAL frequency.
119
120 Bootloaders pre-v2.1 don't do this.
121 */
122 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
123 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
124 ESP_EARLY_LOGW(TAG, "RTC domain not initialised by bootloader");
125 bootloader_clock_configure();
126 }
127 #else
128 /* If this assertion fails, either upgrade the bootloader or enable CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
129 assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
130 #endif
131
132 bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
133 rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
134 rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
135
136 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
137 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
138 // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
139 // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
140 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
141 // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
142 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
143 uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
144 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
145 wdt_hal_feed(&rtc_wdt_ctx);
146 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
147 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
148 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
149 #endif
150
151 #if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
152 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
153 #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
154 select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
155 #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
156 select_rtc_slow_clk(SLOW_CLK_8MD256);
157 #else
158 select_rtc_slow_clk(SLOW_CLK_150K);
159 #endif
160
161 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
162 // After changing a frequency WDT timeout needs to be set for new frequency.
163 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
164 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
165 wdt_hal_feed(&rtc_wdt_ctx);
166 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
167 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
168 #endif
169
170 rtc_cpu_freq_config_t old_config;
171 rtc_cpu_freq_config_t new_config;
172 rtc_clk_cpu_freq_get_config(&old_config);
173 const uint32_t old_freq_mhz = old_config.freq_mhz;
174 const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
175
176 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
177 assert(res);
178
179 // Wait for UART TX to finish, otherwise some UART output will be lost
180 // when switching APB frequency
181 if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
182 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
183 }
184
185 if (res) {
186 rtc_clk_cpu_freq_set_config(&new_config);
187 }
188
189 // Re calculate the ccount to make time calculation correct.
190 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
191 }
192
193 /* This function is not exposed as an API at this point.
194 * All peripheral clocks are default enabled after chip is powered on.
195 * This function disables some peripheral clocks when cpu starts.
196 * These peripheral clocks are enabled when the peripherals are initialized
197 * and disabled when they are de-initialized.
198 */
esp_perip_clk_init(void)199 __attribute__((weak)) void esp_perip_clk_init(void)
200 {
201 uint32_t common_perip_clk;
202 uint32_t hwcrypto_perip_clk;
203 uint32_t wifi_bt_sdio_clk;
204
205 #if CONFIG_FREERTOS_UNICORE
206 soc_reset_reason_t rst_reas[1];
207 #else
208 soc_reset_reason_t rst_reas[2];
209 #endif
210
211 rst_reas[0] = esp_rom_get_reset_reason(0);
212 #if !CONFIG_FREERTOS_UNICORE
213 rst_reas[1] = esp_rom_get_reset_reason(1);
214 #endif
215
216 /* For reason that only reset CPU, do not disable the clocks
217 * that have been enabled before reset.
218 */
219 if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT)
220 #if !CONFIG_FREERTOS_UNICORE
221 || (rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_SW || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT)
222 #endif
223 ) {
224 common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
225 hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
226 wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
227 }
228 else {
229 common_perip_clk = DPORT_WDG_CLK_EN |
230 DPORT_PCNT_CLK_EN |
231 DPORT_LEDC_CLK_EN |
232 DPORT_TIMERGROUP1_CLK_EN |
233 DPORT_PWM0_CLK_EN |
234 DPORT_TWAI_CLK_EN |
235 DPORT_PWM1_CLK_EN |
236 DPORT_PWM2_CLK_EN |
237 DPORT_PWM3_CLK_EN;
238 hwcrypto_perip_clk = DPORT_PERI_EN_AES |
239 DPORT_PERI_EN_SHA |
240 DPORT_PERI_EN_RSA |
241 DPORT_PERI_EN_SECUREBOOT;
242 wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
243 DPORT_WIFI_CLK_BT_EN_M |
244 DPORT_WIFI_CLK_UNUSED_BIT5 |
245 DPORT_WIFI_CLK_UNUSED_BIT12 |
246 DPORT_WIFI_CLK_SDIOSLAVE_EN |
247 DPORT_WIFI_CLK_SDIO_HOST_EN |
248 DPORT_WIFI_CLK_EMAC_EN;
249 }
250
251 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
252 common_perip_clk |= DPORT_I2S0_CLK_EN |
253 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
254 DPORT_UART_CLK_EN |
255 #endif
256 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
257 DPORT_UART1_CLK_EN |
258 #endif
259 #if CONFIG_ESP_CONSOLE_UART_NUM != 2
260 DPORT_UART2_CLK_EN |
261 #endif
262 DPORT_SPI2_CLK_EN |
263 DPORT_I2C_EXT0_CLK_EN |
264 DPORT_UHCI0_CLK_EN |
265 DPORT_RMT_CLK_EN |
266 DPORT_UHCI1_CLK_EN |
267 DPORT_SPI3_CLK_EN |
268 DPORT_I2C_EXT1_CLK_EN |
269 DPORT_I2S1_CLK_EN |
270 DPORT_SPI_DMA_CLK_EN;
271
272 common_perip_clk &= ~DPORT_SPI01_CLK_EN;
273
274 #if CONFIG_SPIRAM_SPEED_80M
275 //80MHz SPIRAM uses SPI2/SPI3 as well; it's initialized before this is called. Because it is used in
276 //a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'
277 //in a state where it outputs a continuous 80MHz signal. Mask its bit here because we should
278 //not modify that state, regardless of what we calculated earlier.
279 if (spicommon_periph_in_use(HSPI_HOST)) {
280 common_perip_clk &= ~DPORT_SPI2_CLK_EN;
281 }
282 if (spicommon_periph_in_use(VSPI_HOST)) {
283 common_perip_clk &= ~DPORT_SPI3_CLK_EN;
284 }
285 #endif
286
287 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
288 * the current is not reduced when disable I2S clock.
289 */
290 DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(0), I2S_CLKA_ENA);
291 DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(1), I2S_CLKA_ENA);
292
293 /* Disable some peripheral clocks. */
294 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
295 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
296
297 /* Disable hardware crypto clocks. */
298 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk);
299 DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk);
300
301 /* Disable WiFi/BT/SDIO clocks. */
302 DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
303
304 /* Enable RNG clock. */
305 periph_module_enable(PERIPH_RNG_MODULE);
306
307 /* Enable TimerGroup 0 clock to ensure its reference counter will never
308 * be decremented to 0 during normal operation and preventing it from
309 * being disabled.
310 * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
311 * registers (Flashboot protection included) will be reenabled, and some
312 * seconds later, will trigger an unintended reset.
313 */
314 periph_module_enable(PERIPH_TIMG0_MODULE);
315 }
316
rtc_clk_select_rtc_slow_clk(void)317 void rtc_clk_select_rtc_slow_clk(void)
318 {
319 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
320 }
321
