1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6/**
7 *                    ESP32-S3 Linker Script Memory Layout
8 * This file describes the memory layout (memory blocks) by virtual memory addresses.
9 * This linker script is passed through the C preprocessor to include configuration options.
10 * Please use preprocessor features sparingly!
11 * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
12 */
13
14#include "sdkconfig.h"
15#include "ld.common"
16
17/*
18 * 40370000 <- IRAM/Icache -> 40378000 <- D/IRAM (I) -> 403E0000
19 *                            3FC88000 <- D/IRAM (D) -> 3FCF0000 <- DRAM/DCache -> 3FD00000
20 *
21 * Startup code uses the IRAM from 0x403B9000 to 0x403E0000, which is not available for static
22 * memory, but can only be used after app starts.
23 *
24 * D cache use the memory from high address, so when it's configured to 16K/32K, the region
25 * 0x3FCF000 ~ (3FD00000 - DATA_CACHE_SIZE) should be available. This region is not used as
26 * static memory, leaving to the heap.
27 */
28
29#define SRAM_IRAM_START     0x40370000
30#define SRAM_DIRAM_I_START  0x40378000
31#define SRAM_IRAM_END       0x403CC700 /* Please refer to ESP32-S3 bootloader.ld for more information on this */
32#define I_D_SRAM_OFFSET     (SRAM_DIRAM_I_START - SRAM_DRAM_START)
33
34#define SRAM_DRAM_START     0x3FC88000
35#define SRAM_DRAM_END       (SRAM_IRAM_END - I_D_SRAM_OFFSET)  /* 2nd stage bootloader iram_loader_seg start address */
36#define I_D_SRAM_SIZE       (SRAM_DRAM_END - SRAM_DRAM_START)
37
38
39#define ICACHE_SIZE         0x8000
40#define SRAM_IRAM_ORG       (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
41#define SRAM_IRAM_SIZE      (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
42
43#define DCACHE_SIZE         0x10000
44#define SRAM_DRAM_ORG       (SRAM_DRAM_START)
45
46#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
47ASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.")
48#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE
49#else
50#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
51#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
52
53MEMORY
54{
55  /**
56   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
57   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
58   *  are connected to the data port of the CPU and eg allow byte-wise access.
59   */
60
61  /* IRAM for PRO CPU. */
62  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE
63
64#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
65  /* Flash mapped instruction data */
66  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x800000-0x20
67
68  /**
69   * (0x20 offset above is a convenience for the app binary image generation.
70   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
71   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
72   * header. Setting this offset makes it simple to meet the flash cache MMU's
73   * constraint that (paddr % 64KB == vaddr % 64KB).)
74   */
75#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
76
77  /**
78   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
79   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
80   */
81  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
82
83#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
84  /* Flash mapped constant data */
85  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x2000000-0x20
86
87  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
88#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
89
90  /**
91   * RTC fast memory (executable). Persists over deep sleep.
92   */
93  rtc_iram_seg(RWX) :                org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM
94
95  /* We reduced the size of rtc_iram_seg by RESERVE_RTC_MEM value.
96     It reserves the amount of RTC fast memory that we use for this memory segment.
97     This segment is intended for keeping:
98       - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
99       - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
100     The aim of this is to keep data that will not be moved around and have a fixed address.
101  */
102  rtc_reserved_seg(RW) :             org = 0x600fe000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
103
104  /**
105   * RTC slow memory (data accessible). Persists over deep sleep.
106   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
107   */
108#if CONFIG_ULP_COPROC_ENABLED
109  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
110                                     len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM
111#else
112  rtc_slow_seg(RW)  :                org = 0x50000000 , len = 0x2000
113#endif // CONFIG_ULP_COPROC_ENABLED
114  /**
115   * `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region.
116   * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
117   */
118  extern_ram_seg(RWX) :              org = 0x3c000020 , len = 0x2000000-0x20
119}
120
121#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
122/* static data ends at defined address */
123_heap_start = SRAM_DRAM_ORG + DRAM0_0_SEG_LEN;
124#else
125_heap_start = _heap_low_start;
126#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
127
128/* Heap ends at top of dram0_0_seg */
129_heap_end = 0x40000000;
130
131_data_seg_org = ORIGIN(rtc_data_seg);
132
133
134/* RTC fast memory shares the same range for both data and instructions */
135REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
136
137#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
138REGION_ALIAS("rtc_data_location", rtc_data_seg );
139#else
140REGION_ALIAS("rtc_data_location", rtc_slow_seg );
141#endif // CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
142
143#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
144REGION_ALIAS("default_code_seg", iram0_2_seg);
145#else
146REGION_ALIAS("default_code_seg", iram0_0_seg);
147#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
148
149#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
150REGION_ALIAS("default_rodata_seg", drom0_0_seg);
151#else
152REGION_ALIAS("default_rodata_seg", dram0_0_seg);
153#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
154
155/**
156 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
157 *  also be first in the segment.
158 */
159#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
160  ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
161         ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
162#endif
163