1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6/* ESP32S2 Linker Script Memory Layout
7
8   This file describes the memory layout (memory blocks) by virtual memory addresses.
9
10   This linker script is passed through the C preprocessor to include configuration options.
11
12   Please use preprocessor features sparingly!
13   Restrict to simple macros with numeric values, and/or #if/#endif blocks.
14*/
15#include "sdkconfig.h"
16#include "ld.common"
17
18#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
19#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000
20#else
21#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000
22#endif
23
24#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB
25#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0
26#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB
27#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000
28#else
29#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000
30#endif
31
32#define RAM_IRAM_START    0x40020000
33#define RAM_DRAM_START    0x3FFB0000
34
35#define DATA_RAM_END      0x3FFDF000  /* 2nd stage bootloader iram_loader_seg starts at end of block 13 (reclaimed after app boots) */
36
37#define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
38                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)
39
40#define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
41                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)
42
43#define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG
44
45#if CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE
46ASSERT((CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE <= I_D_RAM_SIZE), "Fixed static ram data does not fit.")
47#define DRAM0_0_SEG_LEN CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE
48#else
49#define DRAM0_0_SEG_LEN I_D_RAM_SIZE
50#endif // CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE
51MEMORY
52{
53  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
54  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
55  are connected to the data port of the CPU and eg allow bytewise access. */
56
57  /* IRAM for CPU.*/
58  iram0_0_seg (RX) :                 org = IRAM_ORG, len = I_D_RAM_SIZE
59
60#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
61  /* Even though the segment name is iram, it is actually mapped to flash
62  */
63  iram0_2_seg (RX) :                 org = 0x40080020, len = 0x780000-0x20
64
65  /*
66    (0x20 offset above is a convenience for the app binary image generation.
67    Flash cache has 64KB pages. The .bin file which is flashed to the chip
68    has a 0x18 byte file header, and each segment has a 0x08 byte segment
69    header. Setting this offset makes it simple to meet the flash cache MMU's
70    constraint that (paddr % 64KB == vaddr % 64KB).)
71  */
72#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
73
74
75  /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */
76  dram0_0_seg (RW) :                 org = DRAM_ORG, len = DRAM0_0_SEG_LEN
77
78#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
79  /* Flash mapped constant data */
80  drom0_0_seg (R) :                  org = 0x3F000020, len = 0x3f0000-0x20
81
82  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
83#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
84
85  /* RTC fast memory (executable). Persists over deep sleep.
86   */
87  rtc_iram_seg(RWX) :                org = 0x40070000, len = 0x2000 - RESERVE_RTC_MEM
88
89  /* RTC slow memory (data accessible). Persists over deep sleep.
90
91     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
92  */
93#if CONFIG_ULP_COPROC_ENABLED
94  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
95                                     len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM
96#else
97  rtc_slow_seg(RW)  :                org = 0x50000000, len = 0x2000
98#endif // CONFIG_ULP_COPROC_ENABLED
99
100  /* RTC fast memory (same block as above, rtc_iram_seg), viewed from data bus */
101  rtc_data_seg(RW) :                 org = 0x3ff9e000, len = 0x2000 - RESERVE_RTC_MEM
102
103  /* We reduced the size of rtc_data_seg and rtc_iram_seg by RESERVE_RTC_MEM value.
104     It reserves the amount of RTC fast memory that we use for this memory segment.
105     This segment is intended for keeping:
106       - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
107       - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
108     The aim of this is to keep data that will not be moved around and have a fixed address.
109  */
110  rtc_reserved_seg(RW) :             org = 0x3ff9e000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
111
112  /* external memory, covers the dport, dram0, dram1 cacheable address space */
113  extern_ram_seg(RWX)  :             org = 0x3F800000,
114                                     len = 0x780000
115}
116
117#if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE)
118/* static data ends at defined address */
119_heap_start = DRAM_ORG + DRAM0_0_SEG_LEN;
120#else
121_heap_start = _heap_low_start;
122#endif
123
124_heap_end = 0x40000000;
125
126_data_seg_org = ORIGIN(rtc_data_seg);
127
128/* The lines below define location alias for .rtc.data section based on Kconfig option.
129   When the option is not defined then use slow memory segment
130   else the data will be placed in fast memory segment */
131#ifndef CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM
132REGION_ALIAS("rtc_data_location", rtc_slow_seg );
133#else
134REGION_ALIAS("rtc_data_location", rtc_data_seg );
135#endif
136
137#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
138  REGION_ALIAS("default_code_seg", iram0_2_seg);
139#else
140  REGION_ALIAS("default_code_seg", iram0_0_seg);
141#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
142
143#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
144  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
145#else
146  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
147#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
148
149
150/**
151 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
152 *  also be first in the segment.
153 */
154#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
155  ASSERT(_rodata_reserved_start == ORIGIN(default_rodata_seg),
156         ".flash.appdesc section must be placed at the beginning of the rodata segment.")
157#endif
158