1/*
2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/**
8 *                    ESP32-C6 Linker Script Memory Layout
9 * This file describes the memory layout (memory blocks) by virtual memory addresses.
10 * This linker script is passed through the C preprocessor to include configuration options.
11 * Please use preprocessor features sparingly!
12 * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
13 */
14
15#include "sdkconfig.h"
16#include "ld.common"
17
18/**
19 * physical memory is mapped twice to the vritual address (IRAM and DRAM).
20 * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
21 */
22#define SRAM_IRAM_START     0x40800000
23#define SRAM_DRAM_START     0x40800000
24
25#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
26#define SRAM_DRAM_END       0x4086E610 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */
27
28#define SRAM_IRAM_ORG       (SRAM_IRAM_START)
29#define SRAM_DRAM_ORG       (SRAM_DRAM_START)
30
31#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG
32
33#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
34/*
35 * IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB
36 */
37#define IDRAM0_2_SEG_SIZE   (CONFIG_MMU_PAGE_SIZE << 8)
38#endif
39
40#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
41
42MEMORY
43{
44  /**
45   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
46   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
47   *  are connected to the data port of the CPU and eg allow byte-wise access.
48   */
49
50  /* IRAM for PRO CPU. */
51  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
52
53#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
54  /* Flash mapped instruction data */
55  irom_seg (RX) :                    org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
56
57  /**
58   * (0x20 offset above is a convenience for the app binary image generation.
59   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
60   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
61   * header. Setting this offset makes it simple to meet the flash cache MMU's
62   * constraint that (paddr % 64KB == vaddr % 64KB).)
63   */
64#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
65
66  /**
67   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
68   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
69   */
70  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
71
72#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
73  /* Flash mapped constant data */
74  drom_seg (R) :                     org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
75
76  /* (See irom_seg for meaning of 0x20 offset in the above.) */
77#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
78
79  /**
80   * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
81   */
82#if CONFIG_ULP_COPROC_ENABLED
83  lp_ram_seg(RW)  :                 org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
84                                    len = 0x4000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM
85#else
86  lp_ram_seg(RW)  :                 org = 0x50000000, len = 0x4000 - RESERVE_RTC_MEM
87#endif // CONFIG_ULP_COPROC_ENABLED
88
89  /* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
90     It reserves the amount of LP memory that we use for this memory segment.
91     This segment is intended for keeping:
92       - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
93       - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
94     The aim of this is to keep data that will not be moved around and have a fixed address.
95  */
96  lp_reserved_seg(RW) :        org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
97}
98
99/* Heap ends at top of dram0_0_seg */
100_heap_end = 0x40000000;
101
102_data_seg_org = ORIGIN(rtc_data_seg);
103
104/**
105 *  The lines below define location alias for .rtc.data section
106 *  C6 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section
107 *  Thus, the following region segments are not configurable like on other targets
108 */
109REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
110REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
111REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
112REGION_ALIAS("rtc_data_location", rtc_iram_seg );
113REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
114
115#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
116  REGION_ALIAS("default_code_seg", irom_seg);
117#else
118  REGION_ALIAS("default_code_seg", iram0_0_seg);
119#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
120
121#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
122  REGION_ALIAS("default_rodata_seg", drom_seg);
123#else
124  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
125#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
126
127/**
128 *  If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
129 *  also be first in the segment.
130 */
131#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
132  ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
133         ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
134#endif
135
136#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
137    ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
138    ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
139#endif
140