1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* Default entry point */
8ENTRY(call_start_cpu0);
9
10SECTIONS
11{
12  /**
13   * RTC fast memory holds RTC wake stub code,
14   * including from any source file named rtc_wake_stub*.c
15   */
16  .rtc.text :
17  {
18    . = ALIGN(4);
19    _rtc_fast_start = ABSOLUTE(.);
20
21    mapping[rtc_text]
22
23    *rtc_wake_stub*.*(.literal .text .literal.* .text.*)
24    *(.rtc_text_end_test)
25
26    /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */
27    . += _esp_memprot_prefetch_pad_size;
28    . = ALIGN(4);
29
30    _rtc_text_end = ABSOLUTE(.);
31  } > rtc_iram_seg
32
33  /**
34   * This section located in RTC FAST Memory area.
35   * It holds data marked with RTC_FAST_ATTR attribute.
36   * See the file "esp_attr.h" for more information.
37   */
38  .rtc.force_fast :
39  {
40    . = ALIGN(4);
41    _rtc_force_fast_start = ABSOLUTE(.);
42
43    mapping[rtc_force_fast]
44
45    *(.rtc.force_fast .rtc.force_fast.*)
46    . = ALIGN(4) ;
47    _rtc_force_fast_end = ABSOLUTE(.);
48  } > rtc_data_seg
49
50  /**
51   * RTC data section holds RTC wake stub
52   * data/rodata, including from any source file
53   * named rtc_wake_stub*.c and the data marked with
54   * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
55   */
56  .rtc.data :
57  {
58    _rtc_data_start = ABSOLUTE(.);
59
60    mapping[rtc_data]
61
62    *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*)
63    _rtc_data_end = ABSOLUTE(.);
64  } > rtc_data_location
65
66  /* RTC bss, from any source file named rtc_wake_stub*.c */
67  .rtc.bss (NOLOAD) :
68  {
69    _rtc_bss_start = ABSOLUTE(.);
70    *rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*)
71    *rtc_wake_stub*.*(COMMON)
72
73    mapping[rtc_bss]
74
75    _rtc_bss_end = ABSOLUTE(.);
76  } > rtc_data_location
77
78  /**
79   * This section holds data that should not be initialized at power up
80   * and will be retained during deep sleep.
81   * User data marked with RTC_NOINIT_ATTR will be placed
82   * into this section. See the file "esp_attr.h" for more information.
83   */
84  .rtc_noinit (NOLOAD):
85  {
86    . = ALIGN(4);
87    _rtc_noinit_start = ABSOLUTE(.);
88    *(.rtc_noinit .rtc_noinit.*)
89    . = ALIGN(4) ;
90    _rtc_noinit_end = ABSOLUTE(.);
91  } > rtc_data_location
92
93  /**
94   * This section located in RTC SLOW Memory area.
95   * It holds data marked with RTC_SLOW_ATTR attribute.
96   * See the file "esp_attr.h" for more information.
97   */
98  .rtc.force_slow :
99  {
100    . = ALIGN(4);
101    _rtc_force_slow_start = ABSOLUTE(.);
102    *(.rtc.force_slow .rtc.force_slow.*)
103    . = ALIGN(4) ;
104    _rtc_force_slow_end = ABSOLUTE(.);
105  } > rtc_slow_seg
106
107  /**
108   * This section holds RTC data that should have fixed addresses.
109   * The data are not initialized at power-up and are retained during deep sleep.
110   */
111  .rtc_reserved (NOLOAD):
112  {
113    . = ALIGN(4);
114    _rtc_reserved_start = ABSOLUTE(.);
115    /* New data can only be added here to ensure existing data are not moved.
116       Because data have adhered to the end of the segment and code is relied on it.
117       >> put new data here << */
118
119    *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
120    KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
121    _rtc_reserved_end = ABSOLUTE(.);
122  } > rtc_reserved_seg
123
124  _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
125  ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
126          "RTC reserved segment data does not fit.")
127
128  /* Get size of rtc slow data based on rtc_data_location alias */
129  _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
130                        ? (_rtc_force_slow_end - _rtc_data_start)
131                        : (_rtc_force_slow_end - _rtc_force_slow_start);
132
133  _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
134                        ? (_rtc_force_fast_end - _rtc_fast_start)
135                        : (_rtc_noinit_end - _rtc_fast_start);
136
137  ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
138          "RTC_SLOW segment data does not fit.")
139
140  ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
141          "RTC_FAST segment data does not fit.")
142
143  .iram0.text :
144  {
145    _iram_start = ABSOLUTE(.);
146    /* Vectors go to start of IRAM */
147    ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
148    KEEP(*(.exception_vectors.text));
149    . = ALIGN(4);
150
151    _invalid_pc_placeholder = ABSOLUTE(.);
152
153    /* Code marked as running out of IRAM */
154    _iram_text_start = ABSOLUTE(.);
155
156    mapping[iram0_text]
157
158  } > iram0_0_seg
159
160  /**
161   * This section is required to skip .iram0.text area because iram0_0_seg and
162   * dram0_0_seg reflect the same address space on different buses.
163   */
164  .dram0.dummy (NOLOAD):
165  {
166    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
167  } > dram0_0_seg
168
169  .dram0.data :
170  {
171    _data_start = ABSOLUTE(.);
172    *(.gnu.linkonce.d.*)
173    *(.data1)
174    __global_pointer$ = . + 0x800;
175    *(.sdata)
176    *(.sdata.*)
177    *(.gnu.linkonce.s.*)
178    *(.gnu.linkonce.s2.*)
179    *(.jcr)
180
181    mapping[dram0_data]
182
183    _data_end = ABSOLUTE(.);
184    . = ALIGN(4);
185  } > dram0_0_seg
186
187  /**
188   * This section holds data that should not be initialized at power up.
189   * The section located in Internal SRAM memory region. The macro _NOINIT
190   * can be used as attribute to place data into this section.
191   * See the "esp_attr.h" file for more information.
192   */
193  .noinit (NOLOAD):
194  {
195    . = ALIGN(4);
196    _noinit_start = ABSOLUTE(.);
197    *(.noinit .noinit.*)
198    . = ALIGN(4) ;
199    _noinit_end = ABSOLUTE(.);
200  } > dram0_0_seg
201
202  /* Shared RAM */
203  .dram0.bss (NOLOAD) :
204  {
205    . = ALIGN (8);
206    _bss_start = ABSOLUTE(.);
207
208    mapping[dram0_bss]
209
210    *(.dynsbss)
211    *(.sbss)
212    *(.sbss.*)
213    *(.gnu.linkonce.sb.*)
214    *(.scommon)
215    *(.sbss2)
216    *(.sbss2.*)
217    *(.gnu.linkonce.sb2.*)
218    *(.dynbss)
219    *(.share.mem)
220    *(.gnu.linkonce.b.*)
221
222    . = ALIGN (8);
223    _bss_end = ABSOLUTE(.);
224  } > dram0_0_seg
225
226  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
227
228  .flash.text :
229  {
230    _stext = .;
231    _instruction_reserved_start = ABSOLUTE(.);  /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */
232    _text_start = ABSOLUTE(.);
233
234    mapping[flash_text]
235
236    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
237    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
238    *(.fini.literal)
239    *(.fini)
240    *(.gnu.version)
241
242    /** CPU will try to prefetch up to 16 bytes of
243      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
244      * safe access to up to 16 bytes after the last real instruction, add
245      * dummy bytes to ensure this
246      */
247    . += _esp_flash_mmap_prefetch_pad_size;
248
249    _text_end = ABSOLUTE(.);
250    _instruction_reserved_end = ABSOLUTE(.);  /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */
251    _etext = .;
252
253    /**
254     * Similar to _iram_start, this symbol goes here so it is
255     * resolved by addr2line in preference to the first symbol in
256     * the flash.text segment.
257     */
258    _flash_cache_start = ABSOLUTE(0);
259  } > default_code_seg
260
261  /**
262   * This dummy section represents the .flash.text section but in default_rodata_seg.
263   * Thus, it must have its alignment and (at least) its size.
264   */
265  .flash_rodata_dummy (NOLOAD):
266  {
267    _flash_rodata_dummy_start = .;
268    /* Start at the same alignment constraint than .flash.text */
269    . = ALIGN(ALIGNOF(.flash.text));
270    /* Create an empty gap as big as .flash.text section */
271    . = . + SIZEOF(.flash.text);
272    /* Prepare the alignment of the section above. Few bytes (0x20) must be
273     * added for the mapping header. */
274    . = ALIGN(_esp_mmu_block_size) + 0x20;
275  } > default_rodata_seg
276
277  .flash.appdesc : ALIGN(0x10)
278  {
279    _rodata_reserved_start = ABSOLUTE(.);  /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */
280    _rodata_start = ABSOLUTE(.);
281
282    *(.rodata_desc .rodata_desc.*)               /* Should be the first.  App version info.        DO NOT PUT ANYTHING BEFORE IT! */
283    *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
284
285    /* Create an empty gap within this section. Thanks to this, the end of this
286     * section will match .flash.rodata's begin address. Thus, both sections
287     * will be merged when creating the final bin image. */
288    . = ALIGN(ALIGNOF(.flash.rodata));
289  } >default_rodata_seg
290
291  .flash.rodata : ALIGN(0x10)
292  {
293    _flash_rodata_start = ABSOLUTE(.);
294
295    mapping[flash_rodata]
296
297    *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
298    *(.gnu.linkonce.r.*)
299    *(.rodata1)
300    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
301    *(.xt_except_table)
302    *(.gcc_except_table .gcc_except_table.*)
303    *(.gnu.linkonce.e.*)
304    *(.gnu.version_r)
305    . = (. + 7) & ~ 3;
306    /*
307     * C++ constructor and destructor tables
308     * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.
309     *
310     * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.
311     * But the init_priority sections will be sorted for iteration in ascending order during startup.
312     * The rest of the init_array sections is sorted for iteration in descending order during startup, however.
313     * Hence a different section is generated for the init_priority functions which is iterated in
314     * ascending order during startup. The corresponding code can be found in startup.c.
315     */
316    __init_priority_array_start = ABSOLUTE(.);
317    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
318    __init_priority_array_end = ABSOLUTE(.);
319    __init_array_start = ABSOLUTE(.);
320    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
321    __init_array_end = ABSOLUTE(.);
322    KEEP (*crtbegin.*(.dtors))
323    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
324    KEEP (*(SORT(.dtors.*)))
325    KEEP (*(.dtors))
326    /* C++ exception handlers table: */
327    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
328    *(.xt_except_desc)
329    *(.gnu.linkonce.h.*)
330    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
331    *(.xt_except_desc_end)
332    *(.dynamic)
333    *(.gnu.version_d)
334    /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
335    soc_reserved_memory_region_start = ABSOLUTE(.);
336    KEEP (*(.reserved_memory_address))
337    soc_reserved_memory_region_end = ABSOLUTE(.);
338    /* System init functions registered via ESP_SYSTEM_INIT_FN */
339    _esp_system_init_fn_array_start = ABSOLUTE(.);
340    KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
341    _esp_system_init_fn_array_end = ABSOLUTE(.);
342    _rodata_end = ABSOLUTE(.);
343    /* Literals are also RO data. */
344    _lit4_start = ABSOLUTE(.);
345    *(*.lit4)
346    *(.lit4.*)
347    *(.gnu.linkonce.lit4.*)
348    _lit4_end = ABSOLUTE(.);
349    . = ALIGN(4);
350    _thread_local_start = ABSOLUTE(.);
351    *(.tdata)
352    *(.tdata.*)
353    *(.tbss)
354    *(.tbss.*)
355    _thread_local_end = ABSOLUTE(.);
356    . = ALIGN(ALIGNOF(.eh_frame));
357  } > default_rodata_seg
358
359  /* Keep this section shall be at least aligned on 4 */
360  .eh_frame : ALIGN(8)
361  {
362    __eh_frame = ABSOLUTE(.);
363    KEEP (*(.eh_frame))
364    __eh_frame_end = ABSOLUTE(.);
365    /* Guarantee that this section and the next one will be merged by making
366     * them adjacent. */
367    . = ALIGN(ALIGNOF(.eh_frame_hdr));
368  } > default_rodata_seg
369
370  /* To avoid any exception in C++ exception frame unwinding code, this section
371   * shall be aligned on 8. */
372  .eh_frame_hdr : ALIGN(8)
373  {
374    __eh_frame_hdr = ABSOLUTE(.);
375    KEEP (*(.eh_frame_hdr))
376    __eh_frame_hdr_end = ABSOLUTE(.);
377  } > default_rodata_seg
378
379  /*
380    This section is a place where we dump all the rodata which aren't used at runtime,
381    so as to avoid binary size increase
382  */
383  .flash.rodata_noload (NOLOAD) :
384  {
385    /*
386      This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address
387      We don't need to include the noload rodata in this section
388    */
389    _rodata_reserved_end = ABSOLUTE(.);
390    . = ALIGN (4);
391    mapping[rodata_noload]
392  } > default_rodata_seg
393
394  /* Marks the end of IRAM code segment */
395  .iram0.text_end (NOLOAD) :
396  {
397    /* iram_end_test section exists for use by Memprot unit tests only */
398    *(.iram_end_test)
399    /* ESP32-C3 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */
400    . += _esp_memprot_prefetch_pad_size;
401    . = ALIGN(_esp_memprot_align_size);
402    _iram_text_end = ABSOLUTE(.);
403  } > iram0_0_seg
404
405  .iram0.data :
406  {
407    . = ALIGN(16);
408    _iram_data_start = ABSOLUTE(.);
409
410    mapping[iram0_data]
411
412    _iram_data_end = ABSOLUTE(.);
413  } > iram0_0_seg
414
415  .iram0.bss (NOLOAD) :
416  {
417    . = ALIGN(16);
418    _iram_bss_start = ABSOLUTE(.);
419
420    mapping[iram0_bss]
421
422    _iram_bss_end = ABSOLUTE(.);
423    . = ALIGN(16);
424    _iram_end = ABSOLUTE(.);
425  } > iram0_0_seg
426
427  /* Marks the end of data, bss and possibly rodata  */
428  .dram0.heap_start (NOLOAD) :
429  {
430    . = ALIGN (16);
431    _heap_start = ABSOLUTE(.);
432  } > dram0_0_seg
433}
434
435ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
436          "IRAM0 segment data does not fit.")
437
438ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
439          "DRAM segment data does not fit.")
440