1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/**
8 *                    ESP32-C3 Linker Script Memory Layout
9 * This file describes the memory layout (memory blocks) by virtual memory addresses.
10 * This linker script is passed through the C preprocessor to include configuration options.
11 * Please use preprocessor features sparingly!
12 * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
13 */
14
15#include "sdkconfig.h"
16#include "ld.common"
17
18/**
19 * physical memory is mapped twice to the vritual address (IRAM and DRAM).
20 * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
21 */
22#define SRAM_IRAM_START     0x4037C000
23#define SRAM_DRAM_START     0x3FC7C000
24#define ICACHE_SIZE         0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
25#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
26#define SRAM_DRAM_END       0x403CE710 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */
27
28#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)
29#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)
30
31#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG
32
33#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
34
35MEMORY
36{
37  /**
38   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
39   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
40   *  are connected to the data port of the CPU and eg allow byte-wise access.
41   */
42
43  /* IRAM for PRO CPU. */
44  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
45
46#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
47  /* Flash mapped instruction data */
48  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x800000-0x20
49
50  /**
51   * (0x20 offset above is a convenience for the app binary image generation.
52   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
53   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
54   * header. Setting this offset makes it simple to meet the flash cache MMU's
55   * constraint that (paddr % 64KB == vaddr % 64KB).)
56   */
57#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
58
59  /**
60   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
61   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
62   */
63  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
64
65#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
66  /* Flash mapped constant data */
67  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x800000-0x20
68
69  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
70#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
71
72  /**
73   * RTC fast memory (executable). Persists over deep sleep.
74   */
75  rtc_iram_seg(RWX) :                org = 0x50000000, len = 0x2000 - RESERVE_RTC_MEM
76
77  /* We reduced the size of rtc_iram_seg by RESERVE_RTC_MEM value.
78     It reserves the amount of RTC fast memory that we use for this memory segment.
79     This segment is intended for keeping:
80       - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
81       - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
82     The aim of this is to keep data that will not be moved around and have a fixed address.
83  */
84  rtc_reserved_seg(RW) :        org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
85}
86
87/* Heap ends at top of dram0_0_seg */
88_heap_end = 0x40000000;
89
90_data_seg_org = ORIGIN(rtc_data_seg);
91
92/**
93 *  The lines below define location alias for .rtc.data section
94 *  As C3 only has RTC fast memory, this is not configurable like on other targets
95 */
96REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
97REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
98REGION_ALIAS("rtc_data_location", rtc_iram_seg );
99
100#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
101  REGION_ALIAS("default_code_seg", iram0_2_seg);
102#else
103  REGION_ALIAS("default_code_seg", iram0_0_seg);
104#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
105
106#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
107  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
108#else
109  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
110#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
111
112/**
113 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
114 *  also be first in the segment.
115 */
116#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
117  ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
118         ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
119#endif
120
121#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
122    ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
123    ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
124#endif
125