1/** 2 * ESP32-C2 Linker Script Memory Layout 3 * This file describes the memory layout (memory blocks) by virtual memory addresses. 4 * This linker script is passed through the C preprocessor to include configuration options. 5 * Please use preprocessor features sparingly! 6 * Restrict to simple macros with numeric values, and/or #if/#endif blocks. 7 */ 8 9#include "sdkconfig.h" 10#include "ld.common" 11 12#define SRAM_IRAM_START 0x4037C000 13#define SRAM_DRAM_START 0x3FCA0000 14#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C2 */ 15#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START + ICACHE_SIZE) 16#define SRAM_DRAM_END 0x403AEB70 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ 17 18#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) 19#define SRAM_DRAM_ORG (SRAM_DRAM_START) 20 21#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG 22 23#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE 24 25MEMORY 26{ 27 /** 28 * All these values assume the flash cache is on, and have the blocks this uses subtracted from the length 29 * of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but 30 * are connected to the data port of the CPU and eg allow byte-wise access. 31 */ 32 33 /* IRAM for PRO CPU. */ 34 iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE 35 36#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS 37 /* Flash mapped instruction data */ 38 iram0_2_seg (RX) : org = 0x42000020, len = 0x400000-0x20 39 40 /** 41 * (0x20 offset above is a convenience for the app binary image generation. 42 * Flash cache has 64KB pages. The .bin file which is flashed to the chip 43 * has a 0x18 byte file header, and each segment has a 0x08 byte segment 44 * header. Setting this offset makes it simple to meet the flash cache MMU's 45 * constraint that (paddr % 64KB == vaddr % 64KB).) 46 */ 47#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS 48 49 /** 50 * Shared data RAM, excluding memory reserved for ROM bss/data/stack. 51 * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. 52 */ 53 dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN 54 55#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS 56 /* Flash mapped constant data */ 57 drom0_0_seg (R) : org = 0x3C000020, len = 0x400000-0x20 58 59 /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ 60#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS 61 62} 63 64/* Heap ends at top of dram0_0_seg */ 65_heap_end = 0x40000000; 66 67 68#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS 69 REGION_ALIAS("default_code_seg", iram0_2_seg); 70#else 71 REGION_ALIAS("default_code_seg", iram0_0_seg); 72#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS 73 74#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS 75 REGION_ALIAS("default_rodata_seg", drom0_0_seg); 76#else 77 REGION_ALIAS("default_rodata_seg", dram0_0_seg); 78#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS 79 80/** 81 * If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must 82 * also be first in the segment. 83 */ 84#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS 85 ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg), 86 ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.") 87#endif 88 89#if CONFIG_ESP_SYSTEM_USE_EH_FRAME 90 ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!"); 91 ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!"); 92#endif 93