1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6/* ESP32 Linker Script Memory Layout
7
8   This file describes the memory layout (memory blocks) as virtual
9   memory addresses.
10
11   esp32.project.ld contains output sections to link compiler output
12   into these memory blocks.
13
14   ***
15
16   This linker script is passed through the C preprocessor to include
17   configuration options.
18
19   Please use preprocessor features sparingly! Restrict
20   to simple macros with numeric values, and/or #if/#endif blocks.
21*/
22#include "sdkconfig.h"
23#include "ld.common"
24
25/* If BT is not built at all */
26#ifndef CONFIG_BTDM_RESERVE_DRAM
27#define CONFIG_BTDM_RESERVE_DRAM 0
28#endif
29
30#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
31
32ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200),
33          "Fixed static ram data does not fit.")
34
35#define DRAM0_0_SEG_LEN CONFIG_ESP32_FIXED_STATIC_RAM_SIZE
36
37#else
38#define DRAM0_0_SEG_LEN 0x2c200
39#endif
40
41#if CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM
42#define SRAM1_IRAM_LEN 0xA000
43#else
44#define SRAM1_IRAM_LEN 0x0
45#endif
46
47
48MEMORY
49{
50  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
51  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
52  are connected to the data port of the CPU and eg allow bytewise access. */
53
54  /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
55  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000 + SRAM1_IRAM_LEN
56
57#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
58  /* Even though the segment name is iram, it is actually mapped to flash
59  */
60  iram0_2_seg (RX) :                 org = 0x400D0020, len = 0x330000-0x20
61
62  /*
63    (0x20 offset above is a convenience for the app binary image generation.
64    Flash cache has 64KB pages. The .bin file which is flashed to the chip
65    has a 0x18 byte file header, and each segment has a 0x08 byte segment
66    header. Setting this offset makes it simple to meet the flash cache MMU's
67    constraint that (paddr % 64KB == vaddr % 64KB).)
68  */
69#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
70
71
72  /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
73
74     Enabling Bluetooth & Trace Memory features in menuconfig will decrease
75     the amount of RAM available.
76
77     Note: Length of this section *should* be 0x50000, and this extra DRAM is available
78     in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
79     additional static memory temporarily cannot be used.
80  */
81  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BTDM_RESERVE_DRAM,
82                                     len = DRAM0_0_SEG_LEN - CONFIG_BTDM_RESERVE_DRAM
83
84#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
85  /* Flash mapped constant data */
86  drom0_0_seg (R) :                  org = 0x3F400020, len = 0x400000-0x20
87
88  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
89#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
90
91  /* RTC fast memory (executable). Persists over deep sleep. */
92  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
93
94  /* RTC fast memory (same block as above, rtc_iram_seg), viewed from data bus */
95  rtc_data_seg(RW) :                 org = 0x3ff80000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
96
97  /* We reduced the size of rtc_iram_seg and rtc_data_seg by ESP_BOOTLOADER_RESERVE_RTC value.
98     It reserves the amount of RTC fast memory that we use for this memory segment.
99     This segment is intended for keeping bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
100     The aim of this is to keep data that will not be moved around and have a fixed address.
101     org = 0x3ff80000 + 0x2000 - ESP_BOOTLOADER_RESERVE_RTC == SOC_RTC_DRAM_HIGH - sizeof(rtc_retain_mem_t)
102  */
103  rtc_fast_reserved_seg(RW) :        org = 0x3ff80000 + 0x2000 - ESP_BOOTLOADER_RESERVE_RTC, len = ESP_BOOTLOADER_RESERVE_RTC
104
105  /* RTC slow memory (data accessible). Persists over deep sleep.
106
107     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
108  */
109#if CONFIG_ULP_COPROC_ENABLED
110  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
111                                     len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM
112#else
113  rtc_slow_seg(RW)  :                org = 0x50000000, len = 0x2000 - RESERVE_RTC_MEM
114#endif // CONFIG_ULP_COPROC_ENABLED
115
116  /* We reduced the size of rtc_slow_seg by RESERVE_RTC_MEM value.
117     It reserves the amount of RTC slow memory that we use for this memory segment.
118     This segment is intended for keeping rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
119     The aim of this is to keep data that will not be moved around and have a fixed address.
120     org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM
121  */
122  rtc_slow_reserved_seg(RW) :        org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
123
124  /* external memory */
125  extern_ram_seg(RWX)  :             org = 0x3F800000,
126                                     len = 0x400000
127}
128
129#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
130/* static data ends at defined address */
131_heap_start = 0x3FFB0000 + DRAM0_0_SEG_LEN;
132#else
133_heap_start = _heap_low_start;
134#endif
135
136_sram1_iram_start = 0x400A0000;
137_sram1_iram_len = ( _iram_end > _sram1_iram_start) ? (_iram_end - _sram1_iram_start) : 0;
138_heap_end = ALIGN(0x40000000 - _sram1_iram_len - 3, 4);
139
140#if CONFIG_ESP32_TRACEMEM_RESERVE_DRAM != 0
141_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
142#endif
143
144
145_data_seg_org = ORIGIN(rtc_data_seg);
146
147/* The lines below define location alias for .rtc.data section based on Kconfig option.
148   When the option is not defined then use slow memory segment
149   else the data will be placed in fast memory segment */
150#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM
151REGION_ALIAS("rtc_data_location", rtc_slow_seg );
152#else
153REGION_ALIAS("rtc_data_location", rtc_data_seg );
154#endif
155
156#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
157  REGION_ALIAS("default_code_seg", iram0_2_seg);
158#else
159  REGION_ALIAS("default_code_seg", iram0_0_seg);
160#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
161
162#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
163  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
164#else
165  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
166#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
167
168/**
169 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
170 *  also be first in the segment.
171 */
172#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
173  ASSERT(_rodata_start == ORIGIN(default_rodata_seg),
174         ".flash.appdesc section must be placed at the beginning of the rodata segment.")
175#endif
176