1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #ifndef _ROM_EFUSE_H_
16 #define _ROM_EFUSE_H_
17 
18 #include <stdint.h>
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
24 /** \defgroup efuse_APIs efuse APIs
25   * @brief     ESP32 efuse read/write APIs
26   * @attention
27   *
28   */
29 
30 /** @addtogroup efuse_APIs
31   * @{
32   */
33 
34 /**
35   * @brief  Do a efuse read operation, to update the efuse value to efuse read registers.
36   *
37   * @param  null
38   *
39   * @return null
40   */
41 void ets_efuse_read_op(void);
42 
43 /**
44   * @brief  Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
45   *
46   * @param  null
47   *
48   * @return null
49   */
50 void ets_efuse_program_op(void);
51 
52 /**
53   * @brief  Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature.
54   *         It can be used to test the external xtal frequency, do not touch this efuse field.
55   *
56   * @param  null
57   *
58   * @return u32: 1 for 100KHZ, range is 0 to 255.
59   */
60 uint32_t ets_efuse_get_8M_clock(void);
61 
62 /**
63   * @brief  Read spi flash pin configuration from Efuse
64   *
65   * @return
66   * - 0 for default SPI pins.
67   * - 1 for default HSPI pins.
68   * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
69   *   EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
70   *   WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
71   */
72 uint32_t ets_efuse_get_spiconfig(void);
73 
74 #define EFUSE_SPICONFIG_SPI_DEFAULTS 0
75 #define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
76 
77 #define EFUSE_SPICONFIG_RET_SPICLK_MASK         0x3f
78 #define EFUSE_SPICONFIG_RET_SPICLK_SHIFT        0
79 #define EFUSE_SPICONFIG_RET_SPICLK(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
80 
81 #define EFUSE_SPICONFIG_RET_SPIQ_MASK           0x3f
82 #define EFUSE_SPICONFIG_RET_SPIQ_SHIFT          6
83 #define EFUSE_SPICONFIG_RET_SPIQ(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
84 
85 #define EFUSE_SPICONFIG_RET_SPID_MASK           0x3f
86 #define EFUSE_SPICONFIG_RET_SPID_SHIFT          12
87 #define EFUSE_SPICONFIG_RET_SPID(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
88 
89 #define EFUSE_SPICONFIG_RET_SPICS0_MASK         0x3f
90 #define EFUSE_SPICONFIG_RET_SPICS0_SHIFT        18
91 #define EFUSE_SPICONFIG_RET_SPICS0(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
92 
93 
94 #define EFUSE_SPICONFIG_RET_SPIHD_MASK          0x3f
95 #define EFUSE_SPICONFIG_RET_SPIHD_SHIFT         24
96 #define EFUSE_SPICONFIG_RET_SPIHD(ret)          (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
97 
98 /**
99   * @brief  A crc8 algorithm used in efuse check.
100   *
101   * @param  unsigned char const *p : Pointer to original data.
102   *
103   * @param  unsigned int len : Data length in byte.
104   *
105   * @return unsigned char: Crc value.
106   */
107 unsigned char esp_crc8(unsigned char const *p, unsigned int len);
108 
109 /**
110   * @}
111   */
112 
113 #ifdef __cplusplus
114 }
115 #endif
116 
117 #endif /* _ROM_EFUSE_H_ */
118