1 /*
2 * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stddef.h>
8 #include <string.h>
9 #include <stdarg.h>
10
11 #include "sdkconfig.h"
12 #include "soc/soc_caps.h"
13
14 #include "esp_err.h"
15 #include "esp_log.h"
16 #include "esp_attr.h"
17 #include "esp_check.h"
18 #include "esp_private/startup_internal.h"
19 #include "esp_private/sleep_retention.h"
20 #include "esp_private/sleep_clock.h"
21 #include "esp_regdma.h"
22
23 #include "soc/pcr_reg.h"
24 #include "modem/modem_syscon_reg.h"
25
26 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
27 #include "modem/modem_lpcon_reg.h"
28 #endif
29
30 static __attribute__((unused)) const char *TAG = "sleep_clock";
31
sleep_clock_system_retention_init(void * arg)32 static esp_err_t sleep_clock_system_retention_init(void *arg)
33 {
34 #if CONFIG_IDF_TARGET_ESP32C6
35 #define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
36 #elif CONFIG_IDF_TARGET_ESP32H2
37 #define N_REGS_PCR() (((PCR_PWDET_SAR_CLK_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
38 #endif
39 const static sleep_retention_entries_config_t pcr_regs_retention[] = {
40 [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
41 [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(1), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
42 #if CONFIG_IDF_TARGET_ESP32H2
43 [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
44 [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
45 #endif
46 };
47
48 esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
49 ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
50 ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
51 return ESP_OK;
52 }
53
54 #if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
sleep_clock_modem_retention_init(void * arg)55 static esp_err_t sleep_clock_modem_retention_init(void *arg)
56 {
57 #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
58 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
59 #define N_REGS_LPCON() (((MODEM_LPCON_MEM_CONF_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1)
60 #endif
61
62 #if SOC_WIFI_SUPPORTED
63 #define MODEM_WIFI_RETENTION_CLOCK (MODEM_SYSCON_CLK_WIFI_APB_FO | MODEM_SYSCON_CLK_FE_APB_FO)
64 #define MODEM_WIFI_RETENTION_CLOCK_MASK (MODEM_SYSCON_CLK_WIFI_APB_FO_M | MODEM_SYSCON_CLK_FE_APB_FO_M)
65 #endif
66
67 const static sleep_retention_entries_config_t modem_regs_retention[] = {
68 { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
69 #if SOC_WIFI_SUPPORTED
70 { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(1), MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG, MODEM_WIFI_RETENTION_CLOCK, MODEM_WIFI_RETENTION_CLOCK_MASK, 0, 0), .owner = ENTRY(0) }, /* WiFi (MAC, BB and FE) retention clock enable */
71 #endif
72 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
73 { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) } /* MODEM LPCON */
74 #endif
75 };
76 #if SOC_WIFI_SUPPORTED
77 const static sleep_retention_entries_config_t modem_retention_clock[] = {
78 [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(0xf0), MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG, 0x0, MODEM_WIFI_RETENTION_CLOCK_MASK, 0, 0), .owner = ENTRY(0) } /* WiFi (MAC, BB and FE) retention clock disable */
79 };
80 #endif
81 esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
82 ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 2 level priority");
83 #if SOC_WIFI_SUPPORTED
84 err = sleep_retention_entries_create(modem_retention_clock, ARRAY_SIZE(modem_retention_clock), REGDMA_LINK_PRI_7, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
85 ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, lowest level priority");
86 #endif
87 ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
88 return ESP_OK;
89 }
90 #endif
91
clock_domain_pd_allowed(void)92 bool IRAM_ATTR clock_domain_pd_allowed(void)
93 {
94 const uint32_t inited_modules = sleep_retention_get_inited_modules();
95 const uint32_t created_modules = sleep_retention_get_created_modules();
96 const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
97
98 /* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
99 * through MODEM_SYSCON, when one or more MODEMs are initialized, it is
100 * necessary to check the state of CLOCK_MODEM to determine MODEM domain on
101 * or off. The clock and reset of digital peripherals are managed through
102 * PCR, with TOP domain similar to MODEM domain. */
103 uint32_t modem_clk_dep_modules = 0;
104 #if SOC_WIFI_SUPPORTED
105 modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC) | BIT(SLEEP_RETENTION_MODULE_WIFI_BB);
106 #endif
107 #if SOC_BT_SUPPORTED
108 modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
109 #endif
110 #if SOC_IEEE802154_SUPPORTED
111 modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
112 #endif
113
114 uint32_t mask = 0;
115 if (inited_modules & sys_clk_dep_modules) {
116 mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
117 }
118 if (inited_modules & modem_clk_dep_modules) {
119 #if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
120 mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
121 #endif
122 }
123 return ((inited_modules & mask) == (created_modules & mask));
124 }
125
126 ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, BIT(0), 106)
127 {
128 sleep_retention_module_init_param_t init_param = {
129 .cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
130 .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
131 };
132 sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
133
134 #if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
135 init_param = (sleep_retention_module_init_param_t) {
136 .cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
137 .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
138 };
139 sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
140 #endif
141 return ESP_OK;
142 }
143
