1 /*
2 * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8 #include "esp_attr.h"
9 #include <stdint.h>
10 #include <zephyr/kernel.h>
11
12 #include "hal/regi2c_ctrl.h"
13 #include "hal/regi2c_ctrl_ll.h"
14 #include "esp_hw_log.h"
15
16 static int mux;
17
18 #define ENTER_CRITICAL_SECTION() do { mux = irq_lock(); } while(0)
19 #define LEAVE_CRITICAL_SECTION() irq_unlock(mux);
20
21 static DRAM_ATTR __attribute__((unused)) const char *TAG = "REGI2C";
22
23 #ifndef BOOTLOADER_BUILD
regi2c_ctrl_read_reg(uint8_t block,uint8_t host_id,uint8_t reg_add)24 uint8_t IRAM_ATTR regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
25 {
26 ENTER_CRITICAL_SECTION();
27 uint8_t value = regi2c_read_reg_raw(block, host_id, reg_add);
28 LEAVE_CRITICAL_SECTION();
29 return value;
30 }
31
regi2c_ctrl_read_reg_mask(uint8_t block,uint8_t host_id,uint8_t reg_add,uint8_t msb,uint8_t lsb)32 uint8_t IRAM_ATTR regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
33 {
34 ENTER_CRITICAL_SECTION();
35 uint8_t value = regi2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb);
36 LEAVE_CRITICAL_SECTION();
37 return value;
38 }
39
regi2c_ctrl_write_reg(uint8_t block,uint8_t host_id,uint8_t reg_add,uint8_t data)40 void IRAM_ATTR regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
41 {
42 ENTER_CRITICAL_SECTION();
43 regi2c_write_reg_raw(block, host_id, reg_add, data);
44 LEAVE_CRITICAL_SECTION();
45 }
46
regi2c_ctrl_write_reg_mask(uint8_t block,uint8_t host_id,uint8_t reg_add,uint8_t msb,uint8_t lsb,uint8_t data)47 void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
48 {
49 ENTER_CRITICAL_SECTION();
50 regi2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
51 LEAVE_CRITICAL_SECTION();
52 }
53 #endif /* BOOTLOADER_BUILD */
54
regi2c_enter_critical(void)55 void IRAM_ATTR regi2c_enter_critical(void)
56 {
57 ENTER_CRITICAL_SECTION();
58 }
59
regi2c_exit_critical(void)60 void IRAM_ATTR regi2c_exit_critical(void)
61 {
62 LEAVE_CRITICAL_SECTION();
63 }
64
65 /**
66 * Restore regi2c analog calibration related configuration registers.
67 * This is a workaround, and is fixed on later chips
68 */
69 #if REGI2C_ANA_CALI_PD_WORKAROUND
70 #include "soc/regi2c_saradc.h"
71
72 static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM];
73
regi2c_analog_cali_reg_read(void)74 void IRAM_ATTR regi2c_analog_cali_reg_read(void)
75 {
76 for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
77 reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i);
78 }
79 }
80
regi2c_analog_cali_reg_write(void)81 void IRAM_ATTR regi2c_analog_cali_reg_write(void)
82 {
83 for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
84 regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]);
85 }
86 }
87 #endif //#if ADC_CALI_PD_WORKAROUND
88
89 /**
90 * REGI2C_SARADC reference count
91 */
92 static int s_i2c_saradc_enable_cnt;
93
regi2c_saradc_enable(void)94 void regi2c_saradc_enable(void)
95 {
96 regi2c_enter_critical();
97 s_i2c_saradc_enable_cnt++;
98 if (s_i2c_saradc_enable_cnt == 1) {
99 regi2c_ctrl_ll_i2c_saradc_enable();
100 }
101 regi2c_exit_critical();
102 }
103
regi2c_saradc_disable(void)104 void regi2c_saradc_disable(void)
105 {
106 regi2c_enter_critical();
107 s_i2c_saradc_enable_cnt--;
108 if (s_i2c_saradc_enable_cnt < 0){
109 regi2c_exit_critical();
110 ESP_HW_LOGE(TAG, "REGI2C_SARADC is already disabled");
111 } else if (s_i2c_saradc_enable_cnt == 0) {
112 regi2c_ctrl_ll_i2c_saradc_disable();
113 }
114 regi2c_exit_critical();
115
116 }
117
