1 /*
2 * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <esp_types.h>
8 #include <stdlib.h>
9 #include <ctype.h>
10 #include <string.h>
11 #include "sdkconfig.h"
12 #include "esp_intr_alloc.h"
13 #include "esp_log.h"
14 #include "esp_pm.h"
15 #include "esp_check.h"
16 #include "esp_heap_caps.h"
17 #include "freertos/FreeRTOS.h"
18 #include "freertos/semphr.h"
19 #include "freertos/timers.h"
20 #include "freertos/ringbuf.h"
21 #include "esp_private/periph_ctrl.h"
22 #include "esp_private/adc_private.h"
23 #include "esp_private/adc_share_hw_ctrl.h"
24 #include "esp_private/sar_periph_ctrl.h"
25 #include "esp_clk_tree.h"
26 #include "driver/gpio.h"
27 #include "esp_adc/adc_continuous.h"
28 #include "hal/adc_types.h"
29 #include "hal/adc_hal.h"
30 #include "hal/dma_types.h"
31 #include "esp_memory_utils.h"
32 #include "adc_continuous_internal.h"
33 //For DMA
34 #if SOC_GDMA_SUPPORTED
35 #include "esp_private/gdma.h"
36 #elif CONFIG_IDF_TARGET_ESP32S2
37 #include "hal/spi_types.h"
38 #include "esp_private/spi_common_internal.h"
39 #elif CONFIG_IDF_TARGET_ESP32
40 #include "hal/i2s_types.h"
41 #include "driver/i2s_types.h"
42 #include "soc/i2s_periph.h"
43 #include "esp_private/i2s_platform.h"
44 #endif
45
46 static const char *ADC_TAG = "adc_continuous";
47
48 #define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
49
50 extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
51 #define ADC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
52 #define ADC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
53
54 #define INTERNAL_BUF_NUM 5
55
56 /*---------------------------------------------------------------
57 ADC Continuous Read Mode (via DMA)
58 ---------------------------------------------------------------*/
59 //Function to address transaction
60 static bool s_adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx);
61
62 #if SOC_GDMA_SUPPORTED
63 static bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data);
64 #else
65 static void adc_dma_intr_handler(void *arg);
66 #endif
67
adc_digi_get_io_num(adc_unit_t adc_unit,uint8_t adc_channel)68 static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
69 {
70 assert(adc_unit < SOC_ADC_PERIPH_NUM);
71 uint8_t adc_n = (adc_unit == ADC_UNIT_1) ? 0 : 1;
72 return adc_channel_io_map[adc_n][adc_channel];
73 }
74
adc_digi_gpio_init(adc_unit_t adc_unit,uint16_t channel_mask)75 static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
76 {
77 esp_err_t ret = ESP_OK;
78 uint64_t gpio_mask = 0;
79 uint32_t n = 0;
80 int8_t io = 0;
81
82 while (channel_mask) {
83 if (channel_mask & 0x1) {
84 io = adc_digi_get_io_num(adc_unit, n);
85 if (io < 0) {
86 return ESP_ERR_INVALID_ARG;
87 }
88 gpio_mask |= BIT64(io);
89 }
90 channel_mask = channel_mask >> 1;
91 n++;
92 }
93
94 gpio_config_t cfg = {
95 .pin_bit_mask = gpio_mask,
96 .mode = GPIO_MODE_DISABLE,
97 };
98 ret = gpio_config(&cfg);
99
100 return ret;
101 }
102
adc_continuous_new_handle(const adc_continuous_handle_cfg_t * hdl_config,adc_continuous_handle_t * ret_handle)103 esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_config, adc_continuous_handle_t *ret_handle)
104 {
105 esp_err_t ret = ESP_OK;
106 ESP_RETURN_ON_FALSE((hdl_config->conv_frame_size % SOC_ADC_DIGI_DATA_BYTES_PER_CONV == 0), ESP_ERR_INVALID_ARG, ADC_TAG, "conv_frame_size should be in multiples of `SOC_ADC_DIGI_DATA_BYTES_PER_CONV`");
107
108 adc_continuous_ctx_t *adc_ctx = heap_caps_calloc(1, sizeof(adc_continuous_ctx_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
109 if (adc_ctx == NULL) {
110 ret = ESP_ERR_NO_MEM;
111 goto cleanup;
112 }
113
114 //ringbuffer storage/struct buffer
115 adc_ctx->ringbuf_storage = heap_caps_calloc(1, hdl_config->max_store_buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
116 adc_ctx->ringbuf_struct = heap_caps_calloc(1, sizeof(StaticRingbuffer_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
117 if (!adc_ctx->ringbuf_storage || !adc_ctx->ringbuf_struct) {
118 ret = ESP_ERR_NO_MEM;
119 goto cleanup;
120 }
121
122 //ringbuffer
123 adc_ctx->ringbuf_hdl = xRingbufferCreateStatic(hdl_config->max_store_buf_size, RINGBUF_TYPE_BYTEBUF, adc_ctx->ringbuf_storage, adc_ctx->ringbuf_struct);
124 if (!adc_ctx->ringbuf_hdl) {
125 ret = ESP_ERR_NO_MEM;
126 goto cleanup;
127 }
128
129 //malloc internal buffer used by DMA
130 adc_ctx->rx_dma_buf = heap_caps_calloc(1, hdl_config->conv_frame_size * INTERNAL_BUF_NUM, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
131 if (!adc_ctx->rx_dma_buf) {
132 ret = ESP_ERR_NO_MEM;
133 goto cleanup;
134 }
135
136 //malloc dma descriptor
137 uint32_t dma_desc_num_per_frame = (hdl_config->conv_frame_size + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
138 uint32_t dma_desc_max_num = dma_desc_num_per_frame * INTERNAL_BUF_NUM;
139 adc_ctx->hal.rx_desc = heap_caps_calloc(1, (sizeof(dma_descriptor_t)) * dma_desc_max_num, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
140 if (!adc_ctx->hal.rx_desc) {
141 ret = ESP_ERR_NO_MEM;
142 goto cleanup;
143 }
144
145 //malloc pattern table
146 adc_ctx->hal_digi_ctrlr_cfg.adc_pattern = calloc(1, SOC_ADC_PATT_LEN_MAX * sizeof(adc_digi_pattern_config_t));
147 if (!adc_ctx->hal_digi_ctrlr_cfg.adc_pattern) {
148 ret = ESP_ERR_NO_MEM;
149 goto cleanup;
150 }
151
152 #if CONFIG_PM_ENABLE
153 ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc_dma", &adc_ctx->pm_lock);
154 if (ret != ESP_OK) {
155 goto cleanup;
156 }
157 #endif //CONFIG_PM_ENABLE
158
159 #if SOC_GDMA_SUPPORTED
160 //alloc rx gdma channel
161 gdma_channel_alloc_config_t rx_alloc_config = {
162 .direction = GDMA_CHANNEL_DIRECTION_RX,
163 };
164 ret = gdma_new_channel(&rx_alloc_config, &adc_ctx->rx_dma_channel);
165 if (ret != ESP_OK) {
166 goto cleanup;
167 }
168 gdma_connect(adc_ctx->rx_dma_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_ADC, 0));
169
170 gdma_strategy_config_t strategy_config = {
171 .auto_update_desc = true,
172 .owner_check = true
173 };
174 gdma_apply_strategy(adc_ctx->rx_dma_channel, &strategy_config);
175
176 gdma_rx_event_callbacks_t cbs = {
177 .on_recv_eof = adc_dma_in_suc_eof_callback
178 };
179 gdma_register_rx_event_callbacks(adc_ctx->rx_dma_channel, &cbs, adc_ctx);
180
181 int dma_chan;
182 gdma_get_channel_id(adc_ctx->rx_dma_channel, &dma_chan);
183
184 #elif CONFIG_IDF_TARGET_ESP32S2
185 //ADC utilises SPI3 DMA on ESP32S2
186 bool spi_success = false;
187 uint32_t dma_chan = 0;
188
189 spi_success = spicommon_periph_claim(SPI3_HOST, "adc");
190 ret = spicommon_dma_chan_alloc(SPI3_HOST, SPI_DMA_CH_AUTO, &dma_chan, &dma_chan);
191 if (ret == ESP_OK) {
192 adc_ctx->spi_host = SPI3_HOST;
193 }
194 if (!spi_success || (adc_ctx->spi_host != SPI3_HOST)) {
195 goto cleanup;
196 }
197
198 ret = esp_intr_alloc(spicommon_irqdma_source_for_host(adc_ctx->spi_host), ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
199 (void *)adc_ctx, &adc_ctx->dma_intr_hdl);
200 if (ret != ESP_OK) {
201 goto cleanup;
202 }
203
204 #elif CONFIG_IDF_TARGET_ESP32
205 //ADC utilises I2S0 DMA on ESP32
206 uint32_t dma_chan = 0;
207 ret = i2s_platform_acquire_occupation(I2S_NUM_0, "adc");
208 if (ret != ESP_OK) {
209 ret = ESP_ERR_NOT_FOUND;
210 goto cleanup;
211 }
212
213 adc_ctx->i2s_host = I2S_NUM_0;
214 ret = esp_intr_alloc(i2s_periph_signal[adc_ctx->i2s_host].irq, ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
215 (void *)adc_ctx, &adc_ctx->dma_intr_hdl);
216 if (ret != ESP_OK) {
217 goto cleanup;
218 }
219 #endif
220
221 adc_hal_dma_config_t config = {
222 #if SOC_GDMA_SUPPORTED
223 .dev = (void *)GDMA_LL_GET_HW(0),
224 #elif CONFIG_IDF_TARGET_ESP32S2
225 .dev = (void *)SPI_LL_GET_HW(adc_ctx->spi_host),
226 #elif CONFIG_IDF_TARGET_ESP32
227 .dev = (void *)I2S_LL_GET_HW(adc_ctx->i2s_host),
228 #endif
229 .eof_desc_num = INTERNAL_BUF_NUM,
230 .eof_step = dma_desc_num_per_frame,
231 .dma_chan = dma_chan,
232 .eof_num = hdl_config->conv_frame_size / SOC_ADC_DIGI_DATA_BYTES_PER_CONV
233 };
234 adc_hal_dma_ctx_config(&adc_ctx->hal, &config);
235
236 adc_ctx->fsm = ADC_FSM_INIT;
237 *ret_handle = adc_ctx;
238
239 adc_apb_periph_claim();
240
241 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
242 adc_hal_calibration_init(ADC_UNIT_1);
243 adc_hal_calibration_init(ADC_UNIT_2);
244 #endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
245
246 return ret;
247
248 cleanup:
249 adc_continuous_deinit(adc_ctx);
250 return ret;
251 }
252
253 #if SOC_GDMA_SUPPORTED
adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan,gdma_event_data_t * event_data,void * user_data)254 static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
255 {
256 assert(event_data);
257 adc_continuous_ctx_t *ctx = (adc_continuous_ctx_t *)user_data;
258 ctx->rx_eof_desc_addr = event_data->rx_eof_desc_addr;
259 return s_adc_dma_intr(user_data);
260 }
261
262 #else
adc_dma_intr_handler(void * arg)263 static IRAM_ATTR void adc_dma_intr_handler(void *arg)
264 {
265 adc_continuous_ctx_t *ctx = (adc_continuous_ctx_t *)arg;
266 bool need_yield = false;
267
268 bool conversion_finish = adc_hal_check_event(&ctx->hal, ADC_HAL_DMA_INTR_MASK);
269 if (conversion_finish) {
270 adc_hal_digi_clr_intr(&ctx->hal, ADC_HAL_DMA_INTR_MASK);
271
272 intptr_t desc_addr = adc_hal_get_desc_addr(&ctx->hal);
273
274 ctx->rx_eof_desc_addr = desc_addr;
275 need_yield = s_adc_dma_intr(ctx);
276 }
277
278 if (need_yield) {
279 portYIELD_FROM_ISR();
280 }
281 }
282 #endif
283
s_adc_dma_intr(adc_continuous_ctx_t * adc_digi_ctx)284 static IRAM_ATTR bool s_adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx)
285 {
286 portBASE_TYPE taskAwoken = 0;
287 bool need_yield = false;
288 BaseType_t ret;
289 adc_hal_dma_desc_status_t status = false;
290 uint8_t *finished_buffer = NULL;
291 uint32_t finished_size = 0;
292
293 while (1) {
294 status = adc_hal_get_reading_result(&adc_digi_ctx->hal, adc_digi_ctx->rx_eof_desc_addr, &finished_buffer, &finished_size);
295 if (status != ADC_HAL_DMA_DESC_VALID) {
296 break;
297 }
298
299 ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, finished_buffer, finished_size, &taskAwoken);
300 need_yield |= (taskAwoken == pdTRUE);
301
302 if (adc_digi_ctx->cbs.on_conv_done) {
303 adc_continuous_evt_data_t edata = {
304 .conv_frame_buffer = finished_buffer,
305 .size = finished_size,
306 };
307 if (adc_digi_ctx->cbs.on_conv_done(adc_digi_ctx, &edata, adc_digi_ctx->user_data)) {
308 need_yield |= true;
309 }
310 }
311
312 if (ret == pdFALSE) {
313 //ringbuffer overflow
314 if (adc_digi_ctx->cbs.on_pool_ovf) {
315 adc_continuous_evt_data_t edata = {};
316 if (adc_digi_ctx->cbs.on_pool_ovf(adc_digi_ctx, &edata, adc_digi_ctx->user_data)) {
317 need_yield |= true;
318 }
319 }
320 }
321 }
322
323 return need_yield;
324 }
325
adc_continuous_start(adc_continuous_handle_t handle)326 esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
327 {
328 ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
329 ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
330
331 //reset ADC digital part to reset ADC sampling EOF counter
332 periph_module_reset(PERIPH_SARADC_MODULE);
333
334 if (handle->pm_lock) {
335 ESP_RETURN_ON_ERROR(esp_pm_lock_acquire(handle->pm_lock), ADC_TAG, "acquire pm_lock failed");
336 }
337
338 handle->fsm = ADC_FSM_STARTED;
339 sar_periph_ctrl_adc_continuous_power_acquire();
340 //reset flags
341 if (handle->use_adc1) {
342 adc_lock_acquire(ADC_UNIT_1);
343 }
344 if (handle->use_adc2) {
345 adc_lock_acquire(ADC_UNIT_2);
346 }
347
348 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
349 if (handle->use_adc1) {
350 adc_set_hw_calibration_code(ADC_UNIT_1, handle->adc1_atten);
351 }
352 if (handle->use_adc2) {
353 adc_set_hw_calibration_code(ADC_UNIT_2, handle->adc2_atten);
354 }
355 #endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
356
357 #if SOC_ADC_ARBITER_SUPPORTED
358 if (handle->use_adc2) {
359 adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
360 adc_hal_arbiter_config(&config);
361 }
362 #endif //#if SOC_ADC_ARBITER_SUPPORTED
363
364 if (handle->use_adc1) {
365 adc_hal_set_controller(ADC_UNIT_1, ADC_HAL_CONTINUOUS_READ_MODE);
366 }
367 if (handle->use_adc2) {
368 adc_hal_set_controller(ADC_UNIT_2, ADC_HAL_CONTINUOUS_READ_MODE);
369 }
370
371 adc_hal_digi_init(&handle->hal);
372 adc_hal_digi_controller_config(&handle->hal, &handle->hal_digi_ctrlr_cfg);
373
374 //start conversion
375 adc_hal_digi_start(&handle->hal, handle->rx_dma_buf);
376
377 return ESP_OK;
378 }
379
adc_continuous_stop(adc_continuous_handle_t handle)380 esp_err_t adc_continuous_stop(adc_continuous_handle_t handle)
381 {
382 ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
383 ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_STARTED, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver is already stopped");
384
385 handle->fsm = ADC_FSM_INIT;
386 //disable the in suc eof intrrupt
387 adc_hal_digi_dis_intr(&handle->hal, ADC_HAL_DMA_INTR_MASK);
388 //clear the in suc eof interrupt
389 adc_hal_digi_clr_intr(&handle->hal, ADC_HAL_DMA_INTR_MASK);
390 //stop ADC
391 adc_hal_digi_stop(&handle->hal);
392
393 #if ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER
394 periph_module_reset(PERIPH_SARADC_MODULE);
395 adc_hal_digi_clr_eof();
396 #endif
397
398 adc_hal_digi_deinit(&handle->hal);
399
400 if (handle->use_adc2) {
401 adc_lock_release(ADC_UNIT_2);
402 }
403 if (handle->use_adc1) {
404 adc_lock_release(ADC_UNIT_1);
405 }
406 sar_periph_ctrl_adc_continuous_power_release();
407
408 //release power manager lock
409 if (handle->pm_lock) {
410 ESP_RETURN_ON_ERROR(esp_pm_lock_release(handle->pm_lock), ADC_TAG, "release pm_lock failed");
411 }
412
413 return ESP_OK;
414 }
415
adc_continuous_read(adc_continuous_handle_t handle,uint8_t * buf,uint32_t length_max,uint32_t * out_length,uint32_t timeout_ms)416 esp_err_t adc_continuous_read(adc_continuous_handle_t handle, uint8_t *buf, uint32_t length_max, uint32_t *out_length, uint32_t timeout_ms)
417 {
418 ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
419 ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_STARTED, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver is already stopped");
420
421 TickType_t ticks_to_wait;
422 esp_err_t ret = ESP_OK;
423 uint8_t *data = NULL;
424 size_t size = 0;
425
426 ticks_to_wait = timeout_ms / portTICK_PERIOD_MS;
427 if (timeout_ms == ADC_MAX_DELAY) {
428 ticks_to_wait = portMAX_DELAY;
429 }
430
431 data = xRingbufferReceiveUpTo(handle->ringbuf_hdl, &size, ticks_to_wait, length_max);
432 if (!data) {
433 ESP_LOGV(ADC_TAG, "No data, increase timeout");
434 ret = ESP_ERR_TIMEOUT;
435 *out_length = 0;
436 return ret;
437 }
438
439 memcpy(buf, data, size);
440 vRingbufferReturnItem(handle->ringbuf_hdl, data);
441 assert((size % 4) == 0);
442 *out_length = size;
443
444 return ret;
445 }
446
adc_continuous_deinit(adc_continuous_handle_t handle)447 esp_err_t adc_continuous_deinit(adc_continuous_handle_t handle)
448 {
449 ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
450 ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver is still running");
451
452 if (handle->ringbuf_hdl) {
453 vRingbufferDelete(handle->ringbuf_hdl);
454 handle->ringbuf_hdl = NULL;
455 free(handle->ringbuf_storage);
456 free(handle->ringbuf_struct);
457 }
458
459 if (handle->pm_lock) {
460 esp_pm_lock_delete(handle->pm_lock);
461 }
462
463 free(handle->rx_dma_buf);
464 free(handle->hal.rx_desc);
465 free(handle->hal_digi_ctrlr_cfg.adc_pattern);
466 #if SOC_GDMA_SUPPORTED
467 gdma_disconnect(handle->rx_dma_channel);
468 gdma_del_channel(handle->rx_dma_channel);
469 #elif CONFIG_IDF_TARGET_ESP32S2
470 esp_intr_free(handle->dma_intr_hdl);
471 spicommon_dma_chan_free(handle->spi_host);
472 spicommon_periph_free(handle->spi_host);
473 #elif CONFIG_IDF_TARGET_ESP32
474 esp_intr_free(handle->dma_intr_hdl);
475 i2s_platform_release_occupation(handle->i2s_host);
476 #endif
477 free(handle);
478 handle = NULL;
479
480 adc_apb_periph_free();
481
482 return ESP_OK;
483 }
484
485 /*---------------------------------------------------------------
486 Digital controller setting
487 ---------------------------------------------------------------*/
adc_continuous_config(adc_continuous_handle_t handle,const adc_continuous_config_t * config)488 esp_err_t adc_continuous_config(adc_continuous_handle_t handle, const adc_continuous_config_t *config)
489 {
490 ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
491 ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
492
493 //Pattern related check
494 ESP_RETURN_ON_FALSE(config->pattern_num <= SOC_ADC_PATT_LEN_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "Max pattern num is %d", SOC_ADC_PATT_LEN_MAX);
495 for (int i = 0; i < config->pattern_num; i++) {
496 ESP_RETURN_ON_FALSE((config->adc_pattern[i].bit_width >= SOC_ADC_DIGI_MIN_BITWIDTH && config->adc_pattern->bit_width <= SOC_ADC_DIGI_MAX_BITWIDTH), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC bitwidth not supported");
497 }
498
499 for (int i = 0; i < config->pattern_num; i++) {
500 #if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
501 //we add this error log to hint users what happened
502 if (SOC_ADC_DIG_SUPPORTED_UNIT(config->adc_pattern[i].unit) == 0) {
503 ESP_LOGE(ADC_TAG, "ADC2 continuous mode is no longer supported, please use ADC1. Search for errata on espressif website for more details. You can enable CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 to force use ADC2");
504 }
505 #endif //CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
506
507 #if !CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3
508 /**
509 * On all continuous mode supported chips, we will always check the unit to see if it's a continuous mode supported unit.
510 * However, on ESP32C3 and ESP32S3, we will jump this check, if `CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` is enabled.
511 */
512 ESP_RETURN_ON_FALSE(SOC_ADC_DIG_SUPPORTED_UNIT(config->adc_pattern[i].unit), ESP_ERR_INVALID_ARG, ADC_TAG, "Only support using ADC1 DMA mode");
513 #endif //#if !CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3
514 }
515
516 ESP_RETURN_ON_FALSE(config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC sampling frequency out of range");
517
518 #if CONFIG_IDF_TARGET_ESP32
519 ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
520 #elif CONFIG_IDF_TARGET_ESP32S2
521 if (config->conv_mode == ADC_CONV_BOTH_UNIT || config->conv_mode == ADC_CONV_ALTER_UNIT) {
522 ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
523 } else if (config->conv_mode == ADC_CONV_SINGLE_UNIT_1 || config->conv_mode == ADC_CONV_SINGLE_UNIT_2) {
524 ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
525 }
526 #else
527 ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
528 #endif
529
530 uint32_t clk_src_freq_hz = 0;
531 esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
532
533 handle->hal_digi_ctrlr_cfg.adc_pattern_len = config->pattern_num;
534 handle->hal_digi_ctrlr_cfg.sample_freq_hz = config->sample_freq_hz;
535 handle->hal_digi_ctrlr_cfg.conv_mode = config->conv_mode;
536 memcpy(handle->hal_digi_ctrlr_cfg.adc_pattern, config->adc_pattern, config->pattern_num * sizeof(adc_digi_pattern_config_t));
537 handle->hal_digi_ctrlr_cfg.clk_src = ADC_DIGI_CLK_SRC_DEFAULT;
538 handle->hal_digi_ctrlr_cfg.clk_src_freq_hz = clk_src_freq_hz;
539
540 const int atten_uninitialized = 999;
541 handle->adc1_atten = atten_uninitialized;
542 handle->adc2_atten = atten_uninitialized;
543 handle->use_adc1 = 0;
544 handle->use_adc2 = 0;
545 uint32_t adc1_chan_mask = 0;
546 uint32_t adc2_chan_mask = 0;
547 for (int i = 0; i < config->pattern_num; i++) {
548 const adc_digi_pattern_config_t *pat = &config->adc_pattern[i];
549 if (pat->unit == ADC_UNIT_1) {
550 handle->use_adc1 = 1;
551 adc1_chan_mask |= BIT(pat->channel);
552
553 if (handle->adc1_atten == atten_uninitialized) {
554 handle->adc1_atten = pat->atten;
555 } else if (handle->adc1_atten != pat->atten) {
556 return ESP_ERR_INVALID_ARG;
557 }
558 } else if (pat->unit == ADC_UNIT_2) {
559 handle->use_adc2 = 1;
560 adc2_chan_mask |= BIT(pat->channel);
561
562 if (handle->adc2_atten == atten_uninitialized) {
563 handle->adc2_atten = pat->atten;
564 } else if (handle->adc2_atten != pat->atten) {
565 return ESP_ERR_INVALID_ARG;
566 }
567 }
568 }
569
570 if (handle->use_adc1) {
571 adc_digi_gpio_init(ADC_UNIT_1, adc1_chan_mask);
572 }
573 if (handle->use_adc2) {
574 adc_digi_gpio_init(ADC_UNIT_2, adc2_chan_mask);
575 }
576
577 return ESP_OK;
578 }
579
adc_continuous_register_event_callbacks(adc_continuous_handle_t handle,const adc_continuous_evt_cbs_t * cbs,void * user_data)580 esp_err_t adc_continuous_register_event_callbacks(adc_continuous_handle_t handle, const adc_continuous_evt_cbs_t *cbs, void *user_data)
581 {
582 ESP_RETURN_ON_FALSE(handle && cbs, ESP_ERR_INVALID_ARG, ADC_TAG, "invalid argument");
583 ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
584
585 #if CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE
586 if (cbs->on_conv_done) {
587 ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_conv_done), ESP_ERR_INVALID_ARG, ADC_TAG, "on_conv_done callback not in IRAM");
588 }
589 if (cbs->on_pool_ovf) {
590 ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_pool_ovf), ESP_ERR_INVALID_ARG, ADC_TAG, "on_pool_ovf callback not in IRAM");
591 }
592 #endif
593
594 handle->cbs.on_conv_done = cbs->on_conv_done;
595 handle->cbs.on_pool_ovf = cbs->on_pool_ovf;
596 handle->user_data = user_data;
597
598 return ESP_OK;
599 }
600
adc_continuous_io_to_channel(int io_num,adc_unit_t * unit_id,adc_channel_t * channel)601 esp_err_t adc_continuous_io_to_channel(int io_num, adc_unit_t *unit_id, adc_channel_t *channel)
602 {
603 return adc_io_to_channel(io_num, unit_id, channel);
604 }
605
adc_continuous_channel_to_io(adc_unit_t unit_id,adc_channel_t channel,int * io_num)606 esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int *io_num)
607 {
608 return adc_channel_to_io(unit_id, channel, io_num);
609 }
610
