1 /*
2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <sys/param.h>
8 #include "sdkconfig.h"
9 #include "esp_log.h"
10 #include "assert.h"
11 #include "esp_efuse_utility.h"
12 #include "soc/efuse_periph.h"
13 #include "hal/efuse_hal.h"
14
15 static const char *TAG = "efuse";
16
17 #ifdef CONFIG_EFUSE_VIRTUAL
18 extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
19 #endif // CONFIG_EFUSE_VIRTUAL
20
21 /*Range addresses to read blocks*/
22 const esp_efuse_range_addr_t range_read_addr_blocks[] = {
23 {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
24 {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
25 {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
26 {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
27 {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
28 {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
29 {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
30 {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
31 {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
32 {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
33 {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
34 };
35
36 static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
37
38 /*Range addresses to write blocks (it is not real regs, it is buffer) */
39 const esp_efuse_range_addr_t range_write_addr_blocks[] = {
40 {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
41 {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
42 {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
43 {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
44 {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
45 {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
46 {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
47 {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
48 {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
49 {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
50 {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
51 };
52
53 #ifndef CONFIG_EFUSE_VIRTUAL
54 // Update Efuse timing configuration
esp_efuse_set_timing(void)55 static esp_err_t esp_efuse_set_timing(void)
56 {
57 // efuse clock is fixed.
58 // An argument (0) is for compatibility and will be ignored.
59 efuse_hal_set_timing(0);
60 return ESP_OK;
61 }
62 #endif // ifndef CONFIG_EFUSE_VIRTUAL
63
64 // Efuse read operation: copies data from physical efuses to efuse read registers.
esp_efuse_utility_clear_program_registers(void)65 void esp_efuse_utility_clear_program_registers(void)
66 {
67 efuse_hal_read();
68 efuse_hal_clear_program_registers();
69 }
70
esp_efuse_utility_check_errors(void)71 esp_err_t esp_efuse_utility_check_errors(void)
72 {
73 return ESP_OK;
74 }
75
76 // Burn values written to the efuse write registers
esp_efuse_utility_burn_chip(void)77 esp_err_t esp_efuse_utility_burn_chip(void)
78 {
79 esp_err_t error = ESP_OK;
80 #ifdef CONFIG_EFUSE_VIRTUAL
81 ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
82 for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
83 int subblock = 0;
84 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
85 virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
86 }
87 }
88 #ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
89 esp_efuse_utility_write_efuses_to_flash();
90 #endif
91 #else // CONFIG_EFUSE_VIRTUAL
92 if (esp_efuse_set_timing() != ESP_OK) {
93 ESP_LOGE(TAG, "Efuse fields are not burnt");
94 } else {
95 // Permanently update values written to the efuse write registers
96 // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
97 for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
98 bool need_burn_block = false;
99 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
100 if (REG_READ(addr_wr_block) != 0) {
101 need_burn_block = true;
102 break;
103 }
104 }
105 if (!need_burn_block) {
106 continue;
107 }
108 if (error) {
109 // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
110 // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
111 ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
112 continue;
113 }
114 efuse_hal_clear_program_registers();
115 if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
116 uint8_t block_rs[12];
117 efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
118 hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
119 }
120 unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
121 unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
122 memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
123
124 uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
125 hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
126 int repeat_burn_op = 1;
127 bool correct_written_data;
128 bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block);
129 if (coding_error_before) {
130 ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
131 }
132 bool coding_error_occurred;
133
134 do {
135 ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
136 efuse_hal_program(num_block); // BURN a block
137
138 bool coding_error_after;
139 for (unsigned i = 0; i < 5; i++) {
140 efuse_hal_read();
141 coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
142 if (coding_error_after == true) {
143 break;
144 }
145 }
146 coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false;
147 if (coding_error_occurred) {
148 ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
149 }
150
151 correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len);
152 if (!correct_written_data || coding_error_occurred) {
153 ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
154 hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
155 }
156
157 } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
158
159 if (coding_error_occurred) {
160 ESP_LOGW(TAG, "Coding error was not fixed");
161 if (num_block == 0) {
162 ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
163 error = ESP_FAIL;
164 }
165 }
166 if (!correct_written_data) {
167 ESP_LOGE(TAG, "Written data are incorrect");
168 error = ESP_FAIL;
169 }
170 }
171 }
172 #endif // CONFIG_EFUSE_VIRTUAL
173 esp_efuse_utility_reset();
174 return error;
175 }
176
177 // After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
178 // This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
179 // The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
180 // They will be filled during the burn operation.
esp_efuse_utility_apply_new_coding_scheme()181 esp_err_t esp_efuse_utility_apply_new_coding_scheme()
182 {
183 // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
184 for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
185 if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
186 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
187 if (REG_READ(addr_wr_block)) {
188 int num_reg = 0;
189 for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
190 if (esp_efuse_utility_read_reg(num_block, num_reg)) {
191 ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
192 return ESP_ERR_CODING;
193 }
194 }
195 break;
196 }
197 }
198 }
199 }
200 return ESP_OK;
201 }
202
