1 2# field_name, | efuse_block, | bit_start, | bit_count, |comment # 3# | (EFUSE_BLK0 | (0..255) | (1-256) | # 4# | EFUSE_BLK1 | | | # 5# | ...) | | | # 6########################################################################## 7# !!!!!!!!!!! # 8# After editing this file, run the command manually "idf.py efuse-common-table" 9# this will generate new source files, next rebuild all the sources. 10# !!!!!!!!!!! # 11 12# This file was generated by regtools.py based on the efuses.yaml file with the version: 369d2d860d34e777c0f7d545a7dfc3c4 13 14WR_DIS, EFUSE_BLK0, 0, 16, [] Efuse write disable mask 15WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS 16WR_DIS.WR_DIS, EFUSE_BLK0, 1, 1, [] wr_dis of WR_DIS 17WR_DIS.FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of FLASH_CRYPT_CNT 18WR_DIS.UART_DOWNLOAD_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of UART_DOWNLOAD_DIS 19WR_DIS.MAC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC 20WR_DIS.MAC_CRC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC 21WR_DIS.DISABLE_APP_CPU, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU 22WR_DIS.DISABLE_BT, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT 23WR_DIS.DIS_CACHE, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE 24WR_DIS.VOL_LEVEL_HP_INV, EFUSE_BLK0, 3, 1, [] wr_dis of VOL_LEVEL_HP_INV 25WR_DIS.CLK8M_FREQ, EFUSE_BLK0, 4, 1, [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ 26WR_DIS.ADC_VREF, EFUSE_BLK0, 4, 1, [] wr_dis of ADC_VREF 27WR_DIS.XPD_SDIO_REG, EFUSE_BLK0, 5, 1, [] wr_dis of XPD_SDIO_REG 28WR_DIS.XPD_SDIO_TIEH, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH 29WR_DIS.XPD_SDIO_FORCE, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE 30WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CLK 31WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_Q 32WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_D 33WR_DIS.SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CS0 34WR_DIS.BLOCK1, EFUSE_BLK0, 7, 1, [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1 35WR_DIS.BLOCK2, EFUSE_BLK0, 8, 1, [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2 36WR_DIS.BLOCK3, EFUSE_BLK0, 9, 1, [WR_DIS.BLK3] wr_dis of BLOCK3 37WR_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC 38WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC 39WR_DIS.ADC1_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_LOW 40WR_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_HIGH 41WR_DIS.ADC2_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_LOW 42WR_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_HIGH 43WR_DIS.SECURE_VERSION, EFUSE_BLK0, 9, 1, [] wr_dis of SECURE_VERSION 44WR_DIS.MAC_VERSION, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION 45WR_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 10, 1, [] wr_dis of BLK3_PART_RESERVE 46WR_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 10, 1, [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG 47WR_DIS.CODING_SCHEME, EFUSE_BLK0, 10, 1, [] wr_dis of CODING_SCHEME 48WR_DIS.KEY_STATUS, EFUSE_BLK0, 10, 1, [] wr_dis of KEY_STATUS 49WR_DIS.ABS_DONE_0, EFUSE_BLK0, 12, 1, [] wr_dis of ABS_DONE_0 50WR_DIS.ABS_DONE_1, EFUSE_BLK0, 13, 1, [] wr_dis of ABS_DONE_1 51WR_DIS.JTAG_DISABLE, EFUSE_BLK0, 14, 1, [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE 52WR_DIS.CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 15, 1, [] wr_dis of CONSOLE_DEBUG_DISABLE 53WR_DIS.DISABLE_DL_ENCRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_ENCRYPT 54WR_DIS.DISABLE_DL_DECRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_DECRYPT 55WR_DIS.DISABLE_DL_CACHE, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_CACHE 56RD_DIS, EFUSE_BLK0, 16, 4, [] Disable reading from BlOCK1-3 57RD_DIS.BLOCK1, EFUSE_BLK0, 16, 1, [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1 58RD_DIS.BLOCK2, EFUSE_BLK0, 17, 1, [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2 59RD_DIS.BLOCK3, EFUSE_BLK0, 18, 1, [RD_DIS.BLK3] rd_dis of BLOCK3 60RD_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC 61RD_DIS.CUSTOM_MAC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC 62RD_DIS.ADC1_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_LOW 63RD_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_HIGH 64RD_DIS.ADC2_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_LOW 65RD_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_HIGH 66RD_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] rd_dis of SECURE_VERSION 67RD_DIS.MAC_VERSION, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION 68RD_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 19, 1, [] rd_dis of BLK3_PART_RESERVE 69RD_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 19, 1, [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG 70RD_DIS.CODING_SCHEME, EFUSE_BLK0, 19, 1, [] rd_dis of CODING_SCHEME 71RD_DIS.KEY_STATUS, EFUSE_BLK0, 19, 1, [] rd_dis of KEY_STATUS 72FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, [] Flash encryption is enabled if this field has an odd number of bits set 73UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, [] Disable UART download mode. Valid for ESP32 V3 and newer; only 74MAC, EFUSE_BLK0, 72, 8, [MAC_FACTORY] MAC address 75, EFUSE_BLK0, 64, 8, [MAC_FACTORY] MAC address 76, EFUSE_BLK0, 56, 8, [MAC_FACTORY] MAC address 77, EFUSE_BLK0, 48, 8, [MAC_FACTORY] MAC address 78, EFUSE_BLK0, 40, 8, [MAC_FACTORY] MAC address 79, EFUSE_BLK0, 32, 8, [MAC_FACTORY] MAC address 80MAC_CRC, EFUSE_BLK0, 80, 8, [MAC_FACTORY_CRC] CRC8 for MAC address 81DISABLE_APP_CPU, EFUSE_BLK0, 96, 1, [CHIP_VER_DIS_APP_CPU] Disables APP CPU 82DISABLE_BT, EFUSE_BLK0, 97, 1, [CHIP_VER_DIS_BT] Disables Bluetooth 83CHIP_PACKAGE_4BIT, EFUSE_BLK0, 98, 1, [CHIP_VER_PKG_4BIT] Chip package identifier #4bit 84DIS_CACHE, EFUSE_BLK0, 99, 1, [CHIP_VER_DIS_CACHE] Disables cache 85SPI_PAD_CONFIG_HD, EFUSE_BLK0, 100, 5, [] read for SPI_pad_config_hd 86CHIP_PACKAGE, EFUSE_BLK0, 105, 3, [CHIP_VER_PKG] Chip package identifier 87CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise 88CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, [] If set; the ESP32's maximum CPU frequency has been rated 89BLK3_PART_RESERVE, EFUSE_BLK0, 110, 1, [] BLOCK3 partially served for ADC calibration data 90CHIP_VER_REV1, EFUSE_BLK0, 111, 1, [] bit is set to 1 for rev1 silicon 91CLK8M_FREQ, EFUSE_BLK0, 128, 8, [CK8M_FREQ] 8MHz clock freq override 92ADC_VREF, EFUSE_BLK0, 136, 5, [] True ADC reference voltage 93XPD_SDIO_REG, EFUSE_BLK0, 142, 1, [] read for XPD_SDIO_REG 94XPD_SDIO_TIEH, EFUSE_BLK0, 143, 1, [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"} 95XPD_SDIO_FORCE, EFUSE_BLK0, 144, 1, [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset 96SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 160, 5, [] Override SD_CLK pad (GPIO6/SPICLK) 97SPI_PAD_CONFIG_Q, EFUSE_BLK0, 165, 5, [] Override SD_DATA_0 pad (GPIO7/SPIQ) 98SPI_PAD_CONFIG_D, EFUSE_BLK0, 170, 5, [] Override SD_DATA_1 pad (GPIO8/SPID) 99SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 175, 5, [] Override SD_CMD pad (GPIO11/SPICS0) 100CHIP_VER_REV2, EFUSE_BLK0, 180, 1, [] 101VOL_LEVEL_HP_INV, EFUSE_BLK0, 182, 2, [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) 102WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, [] 103FLASH_CRYPT_CONFIG, EFUSE_BLK0, 188, 4, [ENCRYPT_CONFIG] Flash encryption config (key tweak bits) 104CODING_SCHEME, EFUSE_BLK0, 192, 2, [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"} 105CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, [] Disable ROM BASIC interpreter fallback 106DISABLE_SDIO_HOST, EFUSE_BLK0, 195, 1, [] 107ABS_DONE_0, EFUSE_BLK0, 196, 1, [] Secure boot V1 is enabled for bootloader image 108ABS_DONE_1, EFUSE_BLK0, 197, 1, [] Secure boot V2 is enabled for bootloader image 109JTAG_DISABLE, EFUSE_BLK0, 198, 1, [DISABLE_JTAG] Disable JTAG 110DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, [] Disable flash encryption in UART bootloader 111DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, [] Disable flash decryption in UART bootloader 112DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, [] Disable flash cache in UART bootloader 113KEY_STATUS, EFUSE_BLK0, 202, 1, [] Usage of efuse block 3 (reserved) 114BLOCK1, EFUSE_BLK1, 0, MAX_BLK_LEN, [ENCRYPT_FLASH_KEY] Flash encryption key 115BLOCK2, EFUSE_BLK2, 0, MAX_BLK_LEN, [SECURE_BOOT_KEY] Security boot key 116CUSTOM_MAC_CRC, EFUSE_BLK3, 0, 8, [MAC_CUSTOM_CRC] CRC8 for custom MAC address 117MAC_CUSTOM, EFUSE_BLK3, 8, 48, [MAC_CUSTOM] Custom MAC address 118ADC1_TP_LOW, EFUSE_BLK3, 96, 7, [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 119ADC1_TP_HIGH, EFUSE_BLK3, 103, 9, [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 120ADC2_TP_LOW, EFUSE_BLK3, 112, 7, [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 121ADC2_TP_HIGH, EFUSE_BLK3, 119, 9, [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 122SECURE_VERSION, EFUSE_BLK3, 128, 32, [] Secure version for anti-rollback 123MAC_VERSION, EFUSE_BLK3, 184, 8, [MAC_CUSTOM_VER] Version of the MAC field {1: "Custom MAC in BLOCK3"} 124
