1 /*
2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include "sdkconfig.h"
7 #include "bootloader_random.h"
8 #include "soc/soc.h"
9 #include "soc/pcr_reg.h"
10 #include "soc/apb_saradc_reg.h"
11 #include "soc/pmu_reg.h"
12 #include "hal/regi2c_ctrl.h"
13 #include "soc/regi2c_saradc.h"
14 #include "esp_log.h"
15
16 static const uint32_t SAR2_CHANNEL = 9;
17 static const uint32_t PATTERN_BIT_WIDTH = 6;
18 static const uint32_t SAR1_ATTEN = 1;
19 static const uint32_t SAR2_ATTEN = 1;
20
bootloader_random_enable(void)21 void bootloader_random_enable(void)
22 {
23 REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
24 REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
25
26 REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
27
28 REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
29
30 // select XTAL clock (40 MHz) source for ADC_CTRL_CLK
31 REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
32
33 REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
34
35 // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
36 SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
37
38 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
39 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1);
40 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1);
41
42 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0X08);
43 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0X66);
44 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0X08);
45 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0X66);
46
47 // create patterns and set them in pattern table
48 uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN;
49 uint32_t pattern_two = SAR1_ATTEN; // we want channel 0 with max attenuation, channel doesn't really matter here
50 uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
51 REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
52
53 // set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
54 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 0);
55
56 // Same as in C3
57 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
58
59 // set timer expiry (timer is ADC_CTRL_CLK)
60 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
61
62 // ENABLE_TIMER
63 REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
64 }
65
bootloader_random_disable(void)66 void bootloader_random_disable(void)
67 {
68 // disable timer
69 REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
70
71 // Write reset value of this register
72 REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
73
74 // Revert ADC I2C configuration and initial voltage source setting
75 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0x60);
76 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0x0);
77 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0x60);
78 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0x0);
79 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
80 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 0);
81 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 0);
82
83 // disable ADC_CTRL_CLK (SAR ADC function clock)
84 REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
85
86 // Set PCR_SARADC_CONF_REG to initial state
87 REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
88 }
89
