1 /* 2 * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: GPL-2.0-or-later 5 */ 6 7 /* SoC-level support. 8 * 9 * Provide a unified register-level interface. 10 * 11 * This is the same information provided in the register headers 12 * of ESP8266 Non-OS SDK and ESP-IDF soc component, however 13 * only values that are needed for the flasher stub are included here. 14 * 15 */ 16 #pragma once 17 18 #include <stdint.h> 19 #include <stdbool.h> 20 #include <stddef.h> 21 22 #define READ_REG(REG) (*((volatile uint32_t *)(REG))) 23 #define WRITE_REG(REG, VAL) *((volatile uint32_t *)(REG)) = (VAL) 24 #define REG_SET_MASK(reg, mask) WRITE_REG((reg), (READ_REG(reg)|(mask))) 25 #define REG_CLR_MASK(reg, mask) WRITE_REG((reg), (READ_REG(reg)&(~(mask)))) 26 #define REG_SET_FIELD(_r, _f, _v) (WRITE_REG((_r),((READ_REG(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S))))) 27 28 #define ESP32_OR_LATER !(ESP8266) 29 #define ESP32S2_OR_LATER !(ESP8266 || ESP32) 30 #define ESP32S3_OR_LATER !(ESP8266 || ESP32 || ESP32S2) 31 32 /********************************************************** 33 * Per-SOC capabilities 34 */ 35 #ifdef ESP32S2 36 #define WITH_USB_OTG 1 37 #endif // ESP32S2 38 39 #ifdef ESP32C3 40 #define WITH_USB_JTAG_SERIAL 1 41 #define IS_RISCV 1 42 #endif // ESP32C3 43 44 #ifdef ESP32S3 45 #define WITH_USB_JTAG_SERIAL 1 46 #define WITH_USB_OTG 1 47 #endif // ESP32S3 48 49 #ifdef ESP32C5BETA3 50 #define WITH_USB_JTAG_SERIAL 1 51 #define IS_RISCV 1 52 #endif // ESP32C5BETA3 53 54 #ifdef ESP32C6 55 #define WITH_USB_JTAG_SERIAL 1 56 #define IS_RISCV 1 57 #endif // ESP32C6 58 59 #ifdef ESP32H2 60 #define WITH_USB_JTAG_SERIAL 1 61 #define IS_RISCV 1 62 #endif // ESP32H2 63 64 #ifdef ESP32P4 65 #define WITH_USB_JTAG_SERIAL 1 66 // TODO: Add support for USB OTG when MP is available 67 // #define WITH_USB_OTG 1 68 #define IS_RISCV 1 69 #endif // ESP32P4 70 71 // Increase CPU freq to speed up read/write operations over USB 72 // Disabled on the S3 due to stability issues, would require dbias adjustment. 73 // https://github.com/espressif/esptool/issues/832, https://github.com/espressif/esptool/issues/808 74 // Disabled for P4 because it is already running on high (360MHz) CPU frequency 75 #define USE_MAX_CPU_FREQ ((WITH_USB_JTAG_SERIAL || WITH_USB_OTG) && !ESP32S3 && !ESP32P4) 76 77 // Later chips don't support ets_efuse_get_spiconfig. 78 #define SUPPORT_CONFIG_SPI (ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 || ESP32C3 || ESP32H2BETA1 || ESP32H2BETA2 || ESP32C6BETA) 79 80 /********************************************************** 81 * Per-SOC based peripheral register base addresses 82 * Sync with reg_base.h in ESP-IDF 83 */ 84 #ifdef ESP8266 85 #define UART_BASE_REG 0x60000000 /* UART0 */ 86 #define SPI_BASE_REG 0x60000200 /* SPI peripheral 0 */ 87 #endif 88 89 #ifdef ESP32 90 #define UART_BASE_REG 0x3ff40000 /* UART0 */ 91 #define SPI_BASE_REG 0x3ff42000 /* SPI peripheral 1, used for SPI flash */ 92 #define SPI0_BASE_REG 0x3ff43000 /* SPI peripheral 0, inner state machine */ 93 #define GPIO_BASE_REG 0x3ff44000 /* GPIO */ 94 #define DR_REG_IO_MUX_BASE 0x3ff49000 95 #endif 96 97 #ifdef ESP32S2 98 #define UART_BASE_REG 0x60000000 /* UART0 */ 99 #define SPI_BASE_REG 0x3f402000 /* SPI peripheral 1, used for SPI flash */ 100 #define SPI0_BASE_REG 0x3f403000 /* SPI peripheral 0, inner state machine */ 101 #define GPIO_BASE_REG 0x3f404000 102 #define USB_BASE_REG 0x60080000 103 #define RTCCNTL_BASE_REG 0x3f408000 104 #define SYSTEM_BASE_REG 0x3F4C0000 105 #define DR_REG_IO_MUX_BASE 0x3f409000 106 #endif 107 108 #ifdef ESP32S3 109 #define UART_BASE_REG 0x60000000 /* UART0 */ 110 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 111 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 112 #define GPIO_BASE_REG 0x60004000 /* GPIO */ 113 #define USB_BASE_REG 0x60080000 114 #define RTCCNTL_BASE_REG 0x60008000 /* RTC Control */ 115 #define USB_DEVICE_BASE_REG 0x60038000 116 #define SYSTEM_BASE_REG 0x600C0000 117 #define DR_REG_IO_MUX_BASE 0x60009000 118 #endif 119 120 #ifdef ESP32S3BETA2 121 #define UART_BASE_REG 0x60000000 /* UART0 */ 122 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 123 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 124 #define GPIO_BASE_REG 0x60004000 /* GPIO */ 125 #define USB_BASE_REG 0x60080000 126 #define RTCCNTL_BASE_REG 0x60008000 /* RTC Control */ 127 #define USB_DEVICE_BASE_REG 0x60038000 128 #define SYSTEM_BASE_REG 0x600C0000 129 #define DR_REG_IO_MUX_BASE 0x60009000 130 #endif 131 132 #ifdef ESP32C3 133 #define UART_BASE_REG 0x60000000 /* UART0 */ 134 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 135 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 136 #define GPIO_BASE_REG 0x60004000 137 #define RTCCNTL_BASE_REG 0x60008000 /* RTC Control */ 138 #define USB_DEVICE_BASE_REG 0x60043000 139 #define SYSTEM_BASE_REG 0x600C0000 140 #define DR_REG_IO_MUX_BASE 0x60009000 141 #endif 142 143 #ifdef ESP32C6BETA 144 #define UART_BASE_REG 0x60000000 /* UART0 */ 145 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 146 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 147 #define GPIO_BASE_REG 0x60004000 148 #define DR_REG_IO_MUX_BASE 0x60009000 149 #endif 150 151 #ifdef ESP32H2BETA1 152 #define UART_BASE_REG 0x60000000 /* UART0 */ 153 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 154 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 155 #define GPIO_BASE_REG 0x60004000 156 #define RTCCNTL_BASE_REG 0x60008000 157 #define DR_REG_IO_MUX_BASE 0x60009000 158 #endif 159 160 #ifdef ESP32H2BETA2 161 #define UART_BASE_REG 0x60000000 /* UART0 */ 162 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 163 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 164 #define GPIO_BASE_REG 0x60004000 165 #define DR_REG_IO_MUX_BASE 0x60009000 166 #endif 167 168 #ifdef ESP32C2 169 #define UART_BASE_REG 0x60000000 /* UART0 */ 170 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 171 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 172 #define GPIO_BASE_REG 0x60004000 173 #define DR_REG_IO_MUX_BASE 0x60009000 174 #endif 175 176 #if ESP32C6 || ESP32C5BETA3 177 #define UART_BASE_REG 0x60000000 /* UART0 */ 178 #define SPI_BASE_REG 0x60003000 /* SPI peripheral 1, used for SPI flash */ 179 #define SPI0_BASE_REG 0x60002000 /* SPI peripheral 0, inner state machine */ 180 #define GPIO_BASE_REG 0x60091000 181 #define USB_DEVICE_BASE_REG 0x6000F000 182 #define DR_REG_PCR_BASE 0x60096000 183 #define DR_REG_LP_WDT_BASE 0x600B1C00 184 #define DR_REG_IO_MUX_BASE 0x60009000 185 #endif 186 187 #ifdef ESP32H2 188 #define UART_BASE_REG 0x60000000 /* UART0 */ 189 #define SPI_BASE_REG 0x60003000 /* SPI peripheral 1, used for SPI flash */ 190 #define SPI0_BASE_REG 0x60002000 /* SPI peripheral 0, inner state machine */ 191 #define GPIO_BASE_REG 0x60091000 192 #define USB_DEVICE_BASE_REG 0x6000F000 193 #define DR_REG_PCR_BASE 0x60096000 194 #define DR_REG_LP_WDT_BASE 0x600B1C00 195 #define DR_REG_IO_MUX_BASE 0x60009000 196 #endif 197 198 #ifdef ESP32P4 199 #define UART_BASE_REG 0x500CA000 /* UART0 */ 200 #define SPI_BASE_REG 0x5008D000 /* SPI peripheral 1, used for SPI flash */ 201 #define SPI0_BASE_REG 0x5008C000 /* SPI peripheral 0, inner state machine */ 202 #define GPIO_BASE_REG 0x500E0000 203 #define USB_DEVICE_BASE_REG 0x500D2000 204 #define DR_REG_LP_WDT_BASE 0x50116000 205 #define DR_REG_IO_MUX_BASE 0x500E1000 206 #endif 207 208 /********************************************************** 209 * UART peripheral 210 * 211 * The features we use are basically the same on all chips 212 * 213 * Only UART0 is used 214 */ 215 #define UART_CLKDIV_REG(X) (UART_BASE_REG + 0x14) 216 #define UART_CLKDIV_M (0x000FFFFF) 217 218 #if ESP32_OR_LATER 219 #define UART_CLKDIV_FRAG_S 20 220 #define UART_CLKDIV_FRAG_V 0xF 221 #endif 222 223 #define UART_FIFO(X) (UART_BASE_REG + 0x00) 224 #define UART_INT_ST(X) (UART_BASE_REG + 0x08) 225 #define UART_INT_ENA(X) (UART_BASE_REG + 0x0C) 226 #define UART_INT_CLR(X) (UART_BASE_REG + 0x10) 227 #define UART_STATUS(X) (UART_BASE_REG + 0x1C) 228 229 #if ESP32S2_OR_LATER && !ESP32C6 && !ESP32H2 230 #define UART_RXFIFO_CNT_M 0x3FF 231 #else 232 #define UART_RXFIFO_CNT_M 0xFF 233 #endif 234 235 #define UART_RXFIFO_FULL_INT_ENA (1<<0) 236 #define UART_RXFIFO_TOUT_INT_ENA (1<<8) 237 238 #define ETS_UART0_INUM 5 239 240 241 /********************************************************** 242 * SPI peripheral 243 * 244 * The features we use are mostly the same on all chips 245 * except for W0 base address & option for 2-byte status command 246 * 247 * Only one SPI peripheral is used (0 on ESP8266, 1 on ESP32). 248 * On ESP32S2 && ESP32S3 this is called SPI_MEM_xxx index 1 249 */ 250 #define SPI_CMD_REG (SPI_BASE_REG + 0x00) 251 #define SPI_FLASH_WREN (1<<30) 252 #define SPI_FLASH_RDSR (1<<27) 253 #define SPI_FLASH_SE (1<<24) 254 #define SPI_FLASH_BE (1<<23) 255 256 #define SPI_ADDR_REG (SPI_BASE_REG + 0x04) 257 258 #define SPI_CTRL_REG (SPI_BASE_REG + 0x08) 259 #if ESP32_OR_LATER 260 #define SPI_WRSR_2B (1<<22) 261 #endif 262 263 #if ESP32S2_OR_LATER 264 #define SPI_RD_STATUS_REG (SPI_BASE_REG + 0x2C) 265 #else 266 #define SPI_RD_STATUS_REG (SPI_BASE_REG + 0x10) 267 #endif 268 269 #ifdef ESP8266 270 #define SPI_W0_REG (SPI_BASE_REG + 0x40) 271 #endif 272 #ifdef ESP32 273 #define SPI_W0_REG (SPI_BASE_REG + 0x80) 274 #endif 275 #if ESP32S2_OR_LATER 276 #define SPI_W0_REG (SPI_BASE_REG + 0x58) 277 #endif 278 279 #if ESP32S2_OR_LATER 280 #define SPI_EXT2_REG (SPI_BASE_REG + 0x54) /* renamed SPI_MEM_FSM_REG */ 281 #else 282 #define SPI_EXT2_REG (SPI_BASE_REG + 0xF8) 283 #endif 284 285 #define SPI_ST 0x7 /* done state value */ 286 287 #ifdef ESP32 288 /* On ESP32 & newer the SPI peripherals are layered 289 * flash, this lets us check the state of the internal 290 * state machine under the SPI flash controller 291 */ 292 #define SPI0_EXT2_REG (SPI0_BASE_REG + 0xF8) 293 #endif 294 #if ESP32S2_OR_LATER 295 #define SPI0_EXT2_REG (SPI0_BASE_REG + 0x54) 296 #endif 297 298 /********************************************************** 299 * GPIO peripheral 300 * 301 * We only need to read the strapping register on ESP32 or later 302 */ 303 #define GPIO_STRAP_REG (GPIO_BASE_REG + 0x38) 304 305 /********************************************************** 306 * USB peripheral 307 */ 308 309 #ifdef ESP32S2 310 #define UART_USB_OTG 2 311 312 #define ETS_USB_INTR_SOURCE 48 313 #define ETS_USB_INUM 9 /* arbitrary level 1 level interrupt */ 314 #endif // ESP32S2 315 316 #ifdef ESP32C3 317 #define UART_USB_JTAG_SERIAL 3 318 319 #define DR_REG_INTERRUPT_CORE0_BASE 0x600c2000 320 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068) /* USB-JTAG-Serial */ 321 322 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 323 #endif // ESP32C3 324 325 #ifdef ESP32S3 326 #define UART_USB_OTG 3 327 #define UART_USB_JTAG_SERIAL 4 328 329 #define DR_REG_INTERRUPT_CORE0_BASE 0x600c2000 330 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098) /* DWC-OTG */ 331 #define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) /* USB-JTAG-Serial */ 332 333 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 334 #endif // ESP32S3 335 336 #if ESP32C6 || ESP32C5BETA3 337 #define UART_USB_JTAG_SERIAL 3 338 339 #define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 340 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xC0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */ 341 342 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 343 #endif // ESP32C6 || ESP32C5BETA3 344 345 #ifdef ESP32H2 346 #define UART_USB_JTAG_SERIAL 3 347 348 #define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 349 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */ 350 351 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 352 #endif // ESP32H2 353 354 #if ESP32P4 355 #define UART_USB_OTG 5 356 #define UART_USB_JTAG_SERIAL 6 357 358 #define DR_REG_INTERRUPT_MATRIX_BASE 0x500D6000 359 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) /* USB-JTAG-Serial, CORE0_USB_DEVICE_INT_MAP_REG */ 360 361 #define CLIC_EXT_INTR_NUM_OFFSET 16 /* For CLIC first 16 interrupts are reserved as internal */ 362 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 363 #endif 364 365 #ifdef WITH_USB_JTAG_SERIAL 366 #define USB_DEVICE_INT_ENA_REG (USB_DEVICE_BASE_REG + 0x010) 367 #define USB_DEVICE_INT_CLR_REG (USB_DEVICE_BASE_REG + 0x014) 368 #define USB_DEVICE_EP1_CONF_REG (USB_DEVICE_BASE_REG + 0x004) 369 #define USB_DEVICE_EP1_REG (USB_DEVICE_BASE_REG + 0x000) 370 #define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR (1<<2) 371 #define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL (1<<2) 372 #define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA (1<<2) 373 #endif // WITH_USB_JTAG_SERIAL 374 375 #define USB_GAHBCFG_REG (USB_BASE_REG + 0x8) 376 #define USB_GLBLLNTRMSK (1 << 0) 377 378 379 /********************************************************** 380 * RTC_CNTL peripheral 381 */ 382 383 #ifdef ESP32S2 384 #define RTC_CNTL_OPTION1_REG (RTCCNTL_BASE_REG + 0x0128) 385 #endif 386 387 #ifdef ESP32S3 388 #define RTC_CNTL_OPTION1_REG (RTCCNTL_BASE_REG + 0x012C) 389 #define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0098) // RTC_CNTL_RTC_WDTCONFIG0_REG 390 #define RTC_CNTL_WDTWPROTECT_REG (RTCCNTL_BASE_REG + 0x00B0) // RTC_CNTL_RTC_WDTWPROTECT_REG 391 #define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00B4) 392 #define RTC_CNTL_SWD_WPROTECT_REG (RTCCNTL_BASE_REG + 0x00B8) 393 #define RTC_CNTL_SWD_WKEY 0x8F1D312A 394 #define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 31) 395 #endif 396 397 #ifdef ESP32C3 398 #define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0090) 399 #define RTC_CNTL_WDTWPROTECT_REG (RTCCNTL_BASE_REG + 0x00A8) 400 #define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00AC) 401 #define RTC_CNTL_SWD_WPROTECT_REG (RTCCNTL_BASE_REG + 0x00B0) 402 #define RTC_CNTL_SWD_WKEY 0x8F1D312A 403 #define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 31) 404 #endif 405 406 #if ESP32C6 || ESP32C5BETA3 || ESP32P4 407 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG 408 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0018) // LP_WDT_RWDT_WPROTECT_REG 409 #define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x001C) // LP_WDT_SWD_CONFIG_REG 410 #define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0020) // LP_WDT_SWD_WPROTECT_REG 411 #define RTC_CNTL_SWD_WKEY 0x50D83AA1 412 #define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 18) 413 #endif 414 415 #ifdef ESP32H2 416 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG 417 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x001C) // LP_WDT_RWDT_WPROTECT_REG 418 #define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x0020) // LP_WDT_SWD_CONFIG_REG 419 #define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0024) // LP_WDT_SWD_WPROTECT_REG 420 #define RTC_CNTL_SWD_WKEY 0x50D83AA1 421 #define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 18) 422 #endif 423 424 #define RTC_CNTL_WDT_WKEY 0x50D83AA1 425 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT (1 << 0) 426 427 /********************************************************** 428 * SYSTEM registers 429 */ 430 431 #ifdef ESP32C3 432 #define SYSTEM_CPU_PER_CONF_REG (SYSTEM_BASE_REG + 0x008) 433 #define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) 434 #define SYSTEM_CPUPERIOD_SEL_V 0x3 435 #define SYSTEM_CPUPERIOD_SEL_S 0 436 #define SYSTEM_CPUPERIOD_MAX 1 // CPU_CLK frequency is 160 MHz 437 438 #define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x058) 439 #define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) 440 #define SYSTEM_SOC_CLK_SEL_V 0x3 441 #define SYSTEM_SOC_CLK_SEL_S 10 442 #define SYSTEM_SOC_CLK_MAX 1 443 #endif // ESP32C3 444 445 #ifdef ESP32S2 446 #define SYSTEM_CPU_PER_CONF_REG (SYSTEM_BASE_REG + 0x018) 447 #define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) 448 #define SYSTEM_CPUPERIOD_SEL_V 0x3 449 #define SYSTEM_CPUPERIOD_SEL_S 0 450 #define SYSTEM_CPUPERIOD_MAX 2 // CPU_CLK frequency is 240 MHz 451 452 #define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x08C) 453 #define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) 454 #define SYSTEM_SOC_CLK_SEL_V 0x3 455 #define SYSTEM_SOC_CLK_SEL_S 10 456 #define SYSTEM_SOC_CLK_MAX 1 457 #endif // ESP32S2 458 459 #ifdef ESP32C5BETA3 460 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) 461 #define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) 462 #define PCR_SOC_CLK_SEL_V 0x3 463 #define PCR_SOC_CLK_SEL_S 16 464 #define PCR_SOC_CLK_MAX 3 // CPU_CLK frequency is 240 MHz (source is PLL_F240_CLK) 465 #endif // ESP32C5BETA3 466 467 #ifdef ESP32C6 468 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) 469 #define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) 470 #define PCR_SOC_CLK_SEL_V 0x3 471 #define PCR_SOC_CLK_SEL_S 16 472 #define PCR_SOC_CLK_MAX 1 // CPU_CLK frequency is 160 MHz (source is PLL_CLK) 473 #endif // ESP32C6 474 475 #ifdef ESP32H2 476 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) 477 #define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) 478 #define PCR_SOC_CLK_SEL_V 0x3 479 #define PCR_SOC_CLK_SEL_S 16 480 #define PCR_SOC_CLK_MAX 1 // CPU_CLK frequency is 160 MHz (source is PLL_CLK) 481 #endif // ESP32H2 482 483 /********************************************************** 484 * Per-SOC security info buffer size 485 */ 486 487 #ifdef ESP32S2 488 #define SECURITY_INFO_BYTES 12 /* doesn't include chip_id and api_version */ 489 #endif // ESP32S2 490 491 #if ESP32S3_OR_LATER 492 #define SECURITY_INFO_BYTES 20 493 #endif // ESP32S3_OR_LATER 494 495 /********************************************************** 496 * Per-SOC address of the rom_spiflash_legacy_funcs symbol in ROM 497 * Can be retrieved with gdb: "info address rom_spiflash_legacy_funcs" 498 */ 499 500 #if ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 501 #define ROM_SPIFLASH_LEGACY 0x3ffae270 502 #endif // ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 503 504 #if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 || ESP32C5BETA3 505 #define ROM_SPIFLASH_LEGACY 0x3fcdfff4 506 #endif // ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 507 508 #if ESP32H2BETA1 || ESP32H2BETA2 509 #define ROM_SPIFLASH_LEGACY 0x3fcdfff0 510 #endif // ESP32H2BETA1 || ESP32H2BETA2 511 512 #if ESP32H2 513 #define ROM_SPIFLASH_LEGACY 0x4084fff0 514 #endif // ESP32H2 515 516 #if ESP32P4 517 #define ROM_SPIFLASH_LEGACY 0x4ff3ffec 518 #endif // ESP32P4 519 520 /********************************************************** 521 * IO-MUX peripheral 522 */ 523 524 #define MCU_SEL 0x7 525 #define MCU_SEL_S 12 526 527 #define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) 528 529 #if ESP32 530 // PERIPHS_IO_MUX_SD_... 531 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x60) 532 #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x68) 533 #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x64) 534 #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x5c) 535 #define FUNC_GPIO 2 536 #endif // ESP32 537 538 #if ESP32S2 539 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x7c) 540 #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x80) 541 #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x84) 542 #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x78) 543 #define FUNC_GPIO 1 544 #endif // ESP32S2 545 546 #if ESP32C3 547 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x40) 548 #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x48) 549 #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x44) 550 #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x3c) 551 #define FUNC_GPIO 1 552 #endif // ESP32C3 553 554 #if ESP32S3 || ESP32S3BETA2 555 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x7c) 556 #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x80) 557 #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x84) 558 #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x78) 559 #define FUNC_GPIO 1 560 #endif // ESP32S3 || ESP32S3BETA2 561 562 #if ESP32C2 563 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x40) 564 #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x48) 565 #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x44) 566 #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x3c) 567 #define FUNC_GPIO 1 568 #endif // ESP32C2 569 570 #if ESP32C6 || ESP32C6BETA || ESP32C5BETA3 571 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x78) 572 #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x68) 573 #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x7c) 574 #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x64) 575 #define FUNC_GPIO 1 576 #endif // ESP32C6 || ESP32C6BETA 577 578 #if ESP32H2 || ESP32H2BETA1 || ESP32H2BETA2 579 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x50) 580 #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x44) 581 #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x54) 582 #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x40) 583 #define FUNC_GPIO 1 584 #endif // ESP32H2 || ESP32H2BETA1 || ESP32H2BETA2 585 586 #if ESP32P4 587 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x7c) 588 #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x80) 589 #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x84) 590 #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x78) 591 #define FUNC_GPIO 1 592 #endif // ESP32P4 593
