1# This file describes eFuses fields and registers for ESP32-H2 chip 2# 3# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 4# 5# SPDX-License-Identifier: GPL-2.0-or-later 6 7import os 8 9import yaml 10 11from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase 12from typing import List 13 14 15class EfuseDefineRegisters(EfuseRegistersBase): 16 EFUSE_MEM_SIZE = 0x01FC + 4 17 18 # EFUSE registers & command/conf values 19 DR_REG_EFUSE_BASE = 0x6001A000 20 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 21 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 22 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 23 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 24 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 25 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 26 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 27 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 28 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C 29 EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 30 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 31 EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188 32 EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C 33 EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 34 EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC 35 EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 36 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 37 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC 38 EFUSE_WRITE_OP_CODE = 0x5A5A 39 EFUSE_READ_OP_CODE = 0x5AA5 40 EFUSE_PGM_CMD_MASK = 0x3 41 EFUSE_PGM_CMD = 0x2 42 EFUSE_READ_CMD = 0x1 43 44 BLOCK_ERRORS = [ 45 # error_reg, err_num_mask, err_num_offs, fail_bit 46 (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 47 (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 48 (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA 49 (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA 50 (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 51 (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 52 (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 53 (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 54 (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 55 (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 56 (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 57 ] 58 59 # EFUSE_WR_TIM_CONF2_REG 60 EFUSE_PWR_OFF_NUM_S = 0 61 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S 62 63 # EFUSE_WR_TIM_CONF1_REG 64 EFUSE_PWR_ON_NUM_S = 8 65 EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S 66 67 # EFUSE_DAC_CONF_REG 68 EFUSE_DAC_CLK_DIV_S = 0 69 EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S 70 71 # EFUSE_DAC_CONF_REG 72 EFUSE_DAC_NUM_S = 9 73 EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S 74 75 76class EfuseDefineBlocks(EfuseBlocksBase): 77 __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE 78 __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG 79 # List of efuse blocks 80 # fmt: off 81 BLOCKS = [ 82 # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose 83 ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), 84 ("MAC_SPI_8M_0", ["BLOCK1"], 1, __base_rd_regs + 0x044, __base_wr_regs, 20, None, 6, None), 85 ("BLOCK_SYS_DATA", ["BLOCK2"], 2, __base_rd_regs + 0x05C, __base_wr_regs, 21, None, 8, None), 86 ("BLOCK_USR_DATA", ["BLOCK3"], 3, __base_rd_regs + 0x07C, __base_wr_regs, 22, None, 8, None), 87 ("BLOCK_KEY0", ["BLOCK4"], 4, __base_rd_regs + 0x09C, __base_wr_regs, 23, 0, 8, "KEY_PURPOSE_0"), 88 ("BLOCK_KEY1", ["BLOCK5"], 5, __base_rd_regs + 0x0BC, __base_wr_regs, 24, 1, 8, "KEY_PURPOSE_1"), 89 ("BLOCK_KEY2", ["BLOCK6"], 6, __base_rd_regs + 0x0DC, __base_wr_regs, 25, 2, 8, "KEY_PURPOSE_2"), 90 ("BLOCK_KEY3", ["BLOCK7"], 7, __base_rd_regs + 0x0FC, __base_wr_regs, 26, 3, 8, "KEY_PURPOSE_3"), 91 ("BLOCK_KEY4", ["BLOCK8"], 8, __base_rd_regs + 0x11C, __base_wr_regs, 27, 4, 8, "KEY_PURPOSE_4"), 92 ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), 93 ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), 94 ] 95 # fmt: on 96 97 def get_burn_block_data_names(self): 98 list_of_names = [] 99 for block in self.BLOCKS: 100 blk = self.get(block) 101 if blk.name: 102 list_of_names.append(blk.name) 103 if blk.alias: 104 for alias in blk.alias: 105 list_of_names.append(alias) 106 return list_of_names 107 108 109class EfuseDefineFields(EfuseFieldsBase): 110 def __init__(self) -> None: 111 # List of efuse fields from TRM the chapter eFuse Controller. 112 self.EFUSES = [] 113 114 self.KEYBLOCKS = [] 115 116 # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 117 self.BLOCK2_CALIBRATION_EFUSES = [] 118 119 self.CALC: List = [] 120 121 dir_name = os.path.dirname(os.path.abspath(__file__)) 122 dir_name, file_name = os.path.split(dir_name) 123 file_name = file_name + ".yaml" 124 dir_name, _ = os.path.split(dir_name) 125 efuse_file = os.path.join(dir_name, "efuse_defs", file_name) 126 efuse_file = efuse_file.replace("esp32h2beta1", "esp32h2") 127 with open(f"{efuse_file}", "r") as r_file: 128 e_desc = yaml.safe_load(r_file) 129 super().__init__(e_desc) 130 131 for i, efuse in enumerate(self.ALL_EFUSES): 132 if efuse.name in [ 133 "BLOCK_USR_DATA", 134 "BLOCK_KEY0", 135 "BLOCK_KEY1", 136 "BLOCK_KEY2", 137 "BLOCK_KEY3", 138 "BLOCK_KEY4", 139 "BLOCK_KEY5", 140 "BLOCK_SYS_DATA2", 141 ]: 142 if efuse.name == "BLOCK_USR_DATA": 143 efuse.bit_len = 256 144 efuse.type = "bytes:32" 145 self.KEYBLOCKS.append(efuse) 146 self.ALL_EFUSES[i] = None 147 148 elif efuse.category == "calibration": 149 self.BLOCK2_CALIBRATION_EFUSES.append(efuse) 150 self.ALL_EFUSES[i] = None 151 152 for efuse in self.ALL_EFUSES: 153 if efuse is not None: 154 self.EFUSES.append(efuse) 155 156 self.ALL_EFUSES = [] 157