1# This file describes eFuses fields and registers for ESP32-C5 chip 2# 3# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD 4# 5# SPDX-License-Identifier: GPL-2.0-or-later 6 7import os 8 9import yaml 10 11from ..mem_definition_base import ( 12 EfuseBlocksBase, 13 EfuseFieldsBase, 14 EfuseRegistersBase, 15 Field, 16) 17 18 19class EfuseDefineRegisters(EfuseRegistersBase): 20 EFUSE_MEM_SIZE = 0x01FC + 4 21 22 # EFUSE registers & command/conf values 23 DR_REG_EFUSE_BASE = 0x600B4800 24 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 25 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 26 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 27 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 28 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 29 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 30 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 31 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 32 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C 33 EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 34 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 35 EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188 36 EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C 37 EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 38 EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC 39 EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 40 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 41 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC 42 EFUSE_WRITE_OP_CODE = 0x5A5A 43 EFUSE_READ_OP_CODE = 0x5AA5 44 EFUSE_PGM_CMD_MASK = 0x3 45 EFUSE_PGM_CMD = 0x2 46 EFUSE_READ_CMD = 0x1 47 48 BLOCK_ERRORS = [ 49 # error_reg, err_num_mask, err_num_offs, fail_bit 50 (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 51 (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 52 (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA 53 (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA 54 (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 55 (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 56 (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 57 (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 58 (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 59 (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 60 (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 61 ] 62 63 # EFUSE_WR_TIM_CONF2_REG 64 EFUSE_PWR_OFF_NUM_S = 0 65 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S 66 67 # EFUSE_WR_TIM_CONF1_REG 68 EFUSE_PWR_ON_NUM_S = 8 69 EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S 70 71 # EFUSE_DAC_CONF_REG 72 EFUSE_DAC_CLK_DIV_S = 0 73 EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S 74 75 # EFUSE_DAC_CONF_REG 76 EFUSE_DAC_NUM_S = 9 77 EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S 78 79 80class EfuseDefineBlocks(EfuseBlocksBase): 81 __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE 82 __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG 83 # List of efuse blocks 84 # fmt: off 85 BLOCKS = [ 86 # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose 87 ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), 88 ("MAC_SPI_8M_0", ["BLOCK1"], 1, __base_rd_regs + 0x044, __base_wr_regs, 20, None, 6, None), 89 ("BLOCK_SYS_DATA", ["BLOCK2"], 2, __base_rd_regs + 0x05C, __base_wr_regs, 21, None, 8, None), 90 ("BLOCK_USR_DATA", ["BLOCK3"], 3, __base_rd_regs + 0x07C, __base_wr_regs, 22, None, 8, None), 91 ("BLOCK_KEY0", ["BLOCK4"], 4, __base_rd_regs + 0x09C, __base_wr_regs, 23, 0, 8, "KEY_PURPOSE_0"), 92 ("BLOCK_KEY1", ["BLOCK5"], 5, __base_rd_regs + 0x0BC, __base_wr_regs, 24, 1, 8, "KEY_PURPOSE_1"), 93 ("BLOCK_KEY2", ["BLOCK6"], 6, __base_rd_regs + 0x0DC, __base_wr_regs, 25, 2, 8, "KEY_PURPOSE_2"), 94 ("BLOCK_KEY3", ["BLOCK7"], 7, __base_rd_regs + 0x0FC, __base_wr_regs, 26, 3, 8, "KEY_PURPOSE_3"), 95 ("BLOCK_KEY4", ["BLOCK8"], 8, __base_rd_regs + 0x11C, __base_wr_regs, 27, 4, 8, "KEY_PURPOSE_4"), 96 ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), 97 ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), 98 ] 99 # fmt: on 100 101 def get_burn_block_data_names(self): 102 list_of_names = [] 103 for block in self.BLOCKS: 104 blk = self.get(block) 105 if blk.name: 106 list_of_names.append(blk.name) 107 if blk.alias: 108 for alias in blk.alias: 109 list_of_names.append(alias) 110 return list_of_names 111 112 113class EfuseDefineFields(EfuseFieldsBase): 114 def __init__(self) -> None: 115 # List of efuse fields from TRM the chapter eFuse Controller. 116 self.EFUSES = [] 117 118 self.KEYBLOCKS = [] 119 120 # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 121 self.BLOCK2_CALIBRATION_EFUSES = [] 122 123 self.CALC = [] 124 125 dir_name = os.path.dirname(os.path.abspath(__file__)) 126 dir_name, file_name = os.path.split(dir_name) 127 file_name = file_name + ".yaml" 128 dir_name, _ = os.path.split(dir_name) 129 efuse_file = os.path.join(dir_name, "efuse_defs", file_name) 130 with open(f"{efuse_file}", "r") as r_file: 131 e_desc = yaml.safe_load(r_file) 132 super().__init__(e_desc) 133 134 for i, efuse in enumerate(self.ALL_EFUSES): 135 if efuse.name in [ 136 "BLOCK_USR_DATA", 137 "BLOCK_KEY0", 138 "BLOCK_KEY1", 139 "BLOCK_KEY2", 140 "BLOCK_KEY3", 141 "BLOCK_KEY4", 142 "BLOCK_KEY5", 143 "BLOCK_SYS_DATA2", 144 ]: 145 if efuse.name == "BLOCK_USR_DATA": 146 efuse.bit_len = 256 147 efuse.type = "bytes:32" 148 self.KEYBLOCKS.append(efuse) 149 self.ALL_EFUSES[i] = None 150 151 elif efuse.category == "calibration": 152 self.BLOCK2_CALIBRATION_EFUSES.append(efuse) 153 self.ALL_EFUSES[i] = None 154 155 f = Field() 156 f.name = "MAC_EUI64" 157 f.block = 1 158 f.bit_len = 64 159 f.type = f"bytes:{f.bit_len // 8}" 160 f.category = "MAC" 161 f.class_type = "mac" 162 f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" 163 self.CALC.append(f) 164 165 for efuse in self.ALL_EFUSES: 166 if efuse is not None: 167 self.EFUSES.append(efuse) 168 169 self.ALL_EFUSES = [] 170