1# This file describes eFuses fields and registers for ESP32-C3 chip
2#
3# SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
4#
5# SPDX-License-Identifier: GPL-2.0-or-later
6
7import os
8
9import yaml
10
11from ..mem_definition_base import (
12    EfuseBlocksBase,
13    EfuseFieldsBase,
14    EfuseRegistersBase,
15    Field,
16)
17
18
19class EfuseDefineRegisters(EfuseRegistersBase):
20    EFUSE_MEM_SIZE = 0x01FC + 4
21
22    # EFUSE registers & command/conf values
23    DR_REG_EFUSE_BASE = 0x60008800
24    EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE
25    EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020
26    EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8
27    EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC
28    EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0
29    EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4
30    EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0
31    EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4
32    EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C
33    EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180
34    EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184
35    EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188
36    EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C
37    EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8
38    EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC
39    EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0
40    EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4
41    EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC
42    EFUSE_WRITE_OP_CODE = 0x5A5A
43    EFUSE_READ_OP_CODE = 0x5AA5
44    EFUSE_PGM_CMD_MASK = 0x3
45    EFUSE_PGM_CMD = 0x2
46    EFUSE_READ_CMD = 0x1
47
48    # this chip has a design error so fail_bit is shifted by one block but err_num is in the correct place
49    BLOCK_FAIL_BIT = [
50        # error_reg,                fail_bit
51        (EFUSE_RD_REPEAT_ERR0_REG, None),  # BLOCK0
52        (EFUSE_RD_RS_ERR0_REG, 7),  # MAC_SPI_8M_0
53        (EFUSE_RD_RS_ERR0_REG, 11),  # BLOCK_SYS_DATA
54        (EFUSE_RD_RS_ERR0_REG, 15),  # BLOCK_USR_DATA
55        (EFUSE_RD_RS_ERR0_REG, 19),  # BLOCK_KEY0
56        (EFUSE_RD_RS_ERR0_REG, 23),  # BLOCK_KEY1
57        (EFUSE_RD_RS_ERR0_REG, 27),  # BLOCK_KEY2
58        (EFUSE_RD_RS_ERR0_REG, 31),  # BLOCK_KEY3
59        (EFUSE_RD_RS_ERR1_REG, 3),  # BLOCK_KEY4
60        (EFUSE_RD_RS_ERR1_REG, 7),  # BLOCK_KEY5
61        (EFUSE_RD_RS_ERR1_REG, None),  # BLOCK_SYS_DATA2
62    ]
63
64    BLOCK_NUM_ERRORS = [
65        # error_reg,               err_num_mask, err_num_offs
66        (EFUSE_RD_REPEAT_ERR0_REG, None, None),  # BLOCK0
67        (EFUSE_RD_RS_ERR0_REG, 0x7, 0),  # MAC_SPI_8M_0
68        (EFUSE_RD_RS_ERR0_REG, 0x7, 4),  # BLOCK_SYS_DATA
69        (EFUSE_RD_RS_ERR0_REG, 0x7, 8),  # BLOCK_USR_DATA
70        (EFUSE_RD_RS_ERR0_REG, 0x7, 12),  # BLOCK_KEY0
71        (EFUSE_RD_RS_ERR0_REG, 0x7, 16),  # BLOCK_KEY1
72        (EFUSE_RD_RS_ERR0_REG, 0x7, 20),  # BLOCK_KEY2
73        (EFUSE_RD_RS_ERR0_REG, 0x7, 24),  # BLOCK_KEY3
74        (EFUSE_RD_RS_ERR0_REG, 0x7, 28),  # BLOCK_KEY4
75        (EFUSE_RD_RS_ERR1_REG, 0x7, 0),  # BLOCK_KEY5
76        (EFUSE_RD_RS_ERR1_REG, 0x7, 4),  # BLOCK_SYS_DATA2
77    ]
78
79    # EFUSE_WR_TIM_CONF2_REG
80    EFUSE_PWR_OFF_NUM_S = 0
81    EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S
82
83    # EFUSE_WR_TIM_CONF1_REG
84    EFUSE_PWR_ON_NUM_S = 8
85    EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S
86
87    # EFUSE_DAC_CONF_REG
88    EFUSE_DAC_CLK_DIV_S = 0
89    EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S
90
91    # EFUSE_DAC_CONF_REG
92    EFUSE_DAC_NUM_S = 9
93    EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S
94
95
96class EfuseDefineBlocks(EfuseBlocksBase):
97    __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE
98    __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG
99    # List of efuse blocks
100    # fmt: off
101    BLOCKS = [
102        # Name,             Alias,     Index,  Read address,           Write address,  Write protect bit, Read protect bit, Len, key_purpose
103        ("BLOCK0",          [],          0,  __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None),
104        ("MAC_SPI_8M_0",    ["BLOCK1"],  1,  __base_rd_regs + 0x044, __base_wr_regs, 20,   None, 6, None),
105        ("BLOCK_SYS_DATA",  ["BLOCK2"],  2,  __base_rd_regs + 0x05C, __base_wr_regs, 21,   None, 8, None),
106        ("BLOCK_USR_DATA",  ["BLOCK3"],  3,  __base_rd_regs + 0x07C, __base_wr_regs, 22,   None, 8, None),
107        ("BLOCK_KEY0",      ["BLOCK4"],  4,  __base_rd_regs + 0x09C, __base_wr_regs, 23,   0,    8, "KEY_PURPOSE_0"),
108        ("BLOCK_KEY1",      ["BLOCK5"],  5,  __base_rd_regs + 0x0BC, __base_wr_regs, 24,   1,    8, "KEY_PURPOSE_1"),
109        ("BLOCK_KEY2",      ["BLOCK6"],  6,  __base_rd_regs + 0x0DC, __base_wr_regs, 25,   2,    8, "KEY_PURPOSE_2"),
110        ("BLOCK_KEY3",      ["BLOCK7"],  7,  __base_rd_regs + 0x0FC, __base_wr_regs, 26,   3,    8, "KEY_PURPOSE_3"),
111        ("BLOCK_KEY4",      ["BLOCK8"],  8,  __base_rd_regs + 0x11C, __base_wr_regs, 27,   4,    8, "KEY_PURPOSE_4"),
112        ("BLOCK_KEY5",      ["BLOCK9"],  9,  __base_rd_regs + 0x13C, __base_wr_regs, 28,   5,    8, "KEY_PURPOSE_5"),
113        ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29,   6,    8, None),
114    ]
115    # fmt: on
116
117    def get_burn_block_data_names(self):
118        list_of_names = []
119        for block in self.BLOCKS:
120            blk = self.get(block)
121            if blk.name:
122                list_of_names.append(blk.name)
123            if blk.alias:
124                for alias in blk.alias:
125                    list_of_names.append(alias)
126        return list_of_names
127
128
129class EfuseDefineFields(EfuseFieldsBase):
130    def __init__(self) -> None:
131        # List of efuse fields from TRM the chapter eFuse Controller.
132        self.EFUSES = []
133
134        self.KEYBLOCKS = []
135
136        # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2
137        self.BLOCK2_CALIBRATION_EFUSES = []
138
139        self.CALC = []
140
141        dir_name = os.path.dirname(os.path.abspath(__file__))
142        dir_name, file_name = os.path.split(dir_name)
143        file_name = file_name + ".yaml"
144        dir_name, _ = os.path.split(dir_name)
145        efuse_file = os.path.join(dir_name, "efuse_defs", file_name)
146        with open(f"{efuse_file}", "r") as r_file:
147            e_desc = yaml.safe_load(r_file)
148        super().__init__(e_desc)
149
150        for i, efuse in enumerate(self.ALL_EFUSES):
151            if efuse.name in [
152                "BLOCK_USR_DATA",
153                "BLOCK_KEY0",
154                "BLOCK_KEY1",
155                "BLOCK_KEY2",
156                "BLOCK_KEY3",
157                "BLOCK_KEY4",
158                "BLOCK_KEY5",
159                "BLOCK_SYS_DATA2",
160            ]:
161                if efuse.name == "BLOCK_USR_DATA":
162                    efuse.bit_len = 256
163                    efuse.type = "bytes:32"
164                self.KEYBLOCKS.append(efuse)
165                self.ALL_EFUSES[i] = None
166
167            elif efuse.category == "calibration":
168                self.BLOCK2_CALIBRATION_EFUSES.append(efuse)
169                self.ALL_EFUSES[i] = None
170
171            # It is not functional, a bug in the hardware
172            elif efuse.name == "JTAG_SEL_ENABLE":
173                self.ALL_EFUSES[i] = None
174
175        f = Field()
176        f.name = "WAFER_VERSION_MINOR"
177        f.block = 0
178        f.bit_len = 4
179        f.type = f"uint:{f.bit_len}"
180        f.category = "identity"
181        f.class_type = "wafer"
182        f.description = "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)"
183        self.CALC.append(f)
184
185        for efuse in self.ALL_EFUSES:
186            if efuse is not None:
187                self.EFUSES.append(efuse)
188
189        self.ALL_EFUSES = []
190