1 /**
2  * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3  *
4  *  SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include <stdint.h>
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 /** Group: SYSTEM TIMER CLK CONTROL REGISTER */
14 /** Type of conf register
15  *  Configure system timer clock
16  */
17 typedef union {
18     struct {
19         /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
20          *  systimer clock force on
21          */
22         uint32_t systimer_clk_fo:1;
23         /** etm_en : R/W; bitpos: [1]; default: 0;
24          *  enable systimer's etm task and event
25          */
26         uint32_t etm_en:1;
27         uint32_t reserved_2:20;
28         /** target2_work_en : R/W; bitpos: [22]; default: 0;
29          *  target2 work enable
30          */
31         uint32_t target2_work_en:1;
32         /** target1_work_en : R/W; bitpos: [23]; default: 0;
33          *  target1 work enable
34          */
35         uint32_t target1_work_en:1;
36         /** target0_work_en : R/W; bitpos: [24]; default: 0;
37          *  target0 work enable
38          */
39         uint32_t target0_work_en:1;
40         /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
41          *  If timer unit1 is stalled when core1 stalled
42          */
43         uint32_t timer_unit1_core1_stall_en:1;
44         /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
45          *  If timer unit1 is stalled when core0 stalled
46          */
47         uint32_t timer_unit1_core0_stall_en:1;
48         /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
49          *  If timer unit0 is stalled when core1 stalled
50          */
51         uint32_t timer_unit0_core1_stall_en:1;
52         /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
53          *  If timer unit0 is stalled when core0 stalled
54          */
55         uint32_t timer_unit0_core0_stall_en:1;
56         /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
57          *  timer unit1 work enable
58          */
59         uint32_t timer_unit1_work_en:1;
60         /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
61          *  timer unit0 work enable
62          */
63         uint32_t timer_unit0_work_en:1;
64         /** clk_en : R/W; bitpos: [31]; default: 0;
65          *  register file clk gating
66          */
67         uint32_t clk_en:1;
68     };
69     uint32_t val;
70 } systimer_conf_reg_t;
71 
72 
73 /** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */
74 /** Type of unit_op register
75  *  system timer unit value update register
76  */
77 typedef union {
78     struct {
79         uint32_t reserved_0: 29;
80         /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
81          *  timer value is sync and valid
82          */
83         uint32_t timer_unit_value_valid: 1;
84         /** timer_unit_update : WT; bitpos: [30]; default: 0;
85          *  update timer_unit
86          */
87         uint32_t timer_unit_update: 1;
88         uint32_t reserved31: 1;
89     };
90     uint32_t val;
91 } systimer_unit_op_reg_t;
92 
93 /** Type of unit_load register
94  *  system timer unit value high and low load register
95  */
96 typedef struct {
97     union {
98         struct {
99             /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
100              *  timer unit load high 20 bit
101              */
102             uint32_t timer_unit_load_hi: 20;
103             uint32_t reserved20: 12;
104         };
105         uint32_t val;
106     } hi;
107     union {
108         struct {
109             /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
110              *  timer unit load low 32 bit
111              */
112             uint32_t timer_unit_load_lo: 32;
113         };
114         uint32_t val;
115     } lo;
116 } systimer_unit_load_val_reg_t;
117 
118 /** Type of unit_value_hi register
119  *  system timer unit value high and low register
120  */
121 typedef struct {
122     union {
123         struct {
124             /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
125              *  timer read value high 20 bit
126              */
127             uint32_t timer_unit_value_hi: 20;
128             uint32_t reserved20: 12;
129         };
130         uint32_t val;
131     } hi;
132     union {
133         struct {
134             /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
135              *  timer read value low 32 bit
136              */
137             uint32_t timer_unit_value_lo: 32;
138         };
139         uint32_t val;
140     } lo;
141 } systimer_unit_value_reg_t;
142 
143 /** Type of unit_load register
144  *  system timer unit conf sync register
145  */
146 typedef union {
147     struct {
148         /** timer_unit_load : WT; bitpos: [0]; default: 0;
149          *  timer unit load value
150          */
151         uint32_t timer_unit_load: 1;
152         uint32_t reserved1: 31;
153     };
154     uint32_t val;
155 } systimer_unit_load_reg_t;
156 
157 
158 /** Group: SYSTEM TIMER COMP CONTROL AND CONFIGURATION REGISTER */
159 /** Type of target register
160  *  system timer comp value high and low register
161  */
162 typedef struct {
163     union {
164         struct {
165             /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
166              *  timer target high 20 bit
167              */
168             uint32_t timer_target_hi: 20;
169             uint32_t reserved20: 12;
170         };
171         uint32_t val;
172     } hi;
173     union {
174         struct {
175             /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
176              *  timer target low 32 bit
177              */
178             uint32_t timer_target_lo: 32;
179         };
180         uint32_t val;
181     } lo;
182 } systimer_target_val_reg_t;
183 
184 /** Type of target_conf register
185  *  system timer comp target mode register
186  */
187 typedef union {
188     struct {
189         /** target_period : R/W; bitpos: [25:0]; default: 0;
190          *  target period
191          */
192         uint32_t target_period: 26;
193         uint32_t reserved_26: 4;
194         /** target_period_mode : R/W; bitpos: [30]; default: 0;
195          *  Set target to period mode
196          */
197         uint32_t target_period_mode: 1;
198         /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
199          *  select which unit to compare
200          */
201         uint32_t target_timer_unit_sel: 1;
202     };
203     uint32_t val;
204 } systimer_target_conf_reg_t;
205 
206 /** Type of comp_load register
207  *  system timer comp conf sync register
208  */
209 typedef union {
210     struct {
211         /** timer_comp_load : WT; bitpos: [0]; default: 0;
212          *  timer comp sync enable signal
213          */
214         uint32_t timer_comp_load: 1;
215         uint32_t reserved1: 31;
216     };
217     uint32_t val;
218 } systimer_comp_load_reg_t;
219 
220 
221 /** Group: SYSTEM TIMER INTERRUPT REGISTER */
222 /** Type of int_ena register
223  *  systimer interrupt enable register
224  */
225 typedef union {
226     struct {
227         /** target0_int_ena : R/W; bitpos: [0]; default: 0;
228          *  interupt0 enable
229          */
230         uint32_t target0_int_ena:1;
231         /** target1_int_ena : R/W; bitpos: [1]; default: 0;
232          *  interupt1 enable
233          */
234         uint32_t target1_int_ena:1;
235         /** target2_int_ena : R/W; bitpos: [2]; default: 0;
236          *  interupt2 enable
237          */
238         uint32_t target2_int_ena:1;
239         uint32_t reserved_3:29;
240     };
241     uint32_t val;
242 } systimer_int_ena_reg_t;
243 
244 /** Type of int_raw register
245  *  systimer interrupt raw register
246  */
247 typedef union {
248     struct {
249         /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
250          *  interupt0 raw
251          */
252         uint32_t target0_int_raw:1;
253         /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
254          *  interupt1 raw
255          */
256         uint32_t target1_int_raw:1;
257         /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
258          *  interupt2 raw
259          */
260         uint32_t target2_int_raw:1;
261         uint32_t reserved_3:29;
262     };
263     uint32_t val;
264 } systimer_int_raw_reg_t;
265 
266 /** Type of int_clr register
267  *  systimer interrupt clear register
268  */
269 typedef union {
270     struct {
271         /** target0_int_clr : WT; bitpos: [0]; default: 0;
272          *  interupt0 clear
273          */
274         uint32_t target0_int_clr:1;
275         /** target1_int_clr : WT; bitpos: [1]; default: 0;
276          *  interupt1 clear
277          */
278         uint32_t target1_int_clr:1;
279         /** target2_int_clr : WT; bitpos: [2]; default: 0;
280          *  interupt2 clear
281          */
282         uint32_t target2_int_clr:1;
283         uint32_t reserved_3:29;
284     };
285     uint32_t val;
286 } systimer_int_clr_reg_t;
287 
288 /** Type of int_st register
289  *  systimer interrupt status register
290  */
291 typedef union {
292     struct {
293         /** target0_int_st : RO; bitpos: [0]; default: 0;
294          *  interupt0 status
295          */
296         uint32_t target0_int_st:1;
297         /** target1_int_st : RO; bitpos: [1]; default: 0;
298          *  interupt1 status
299          */
300         uint32_t target1_int_st:1;
301         /** target2_int_st : RO; bitpos: [2]; default: 0;
302          *  interupt2 status
303          */
304         uint32_t target2_int_st:1;
305         uint32_t reserved_3:29;
306     };
307     uint32_t val;
308 } systimer_int_st_reg_t;
309 
310 
311 /** Group: SYSTEM TIMER COMP STATUS REGISTER */
312 /** Type of real_target_hi/lo register
313  *  system timer comp actual target value low register
314  */
315 typedef struct {
316     union {
317         struct {
318             /** target_lo_ro : RO; bitpos: [31:0]; default: 0;
319              *  actual target value value low 32 bits
320              */
321             uint32_t target_lo_ro: 32;
322         };
323         uint32_t val;
324     } lo;
325     union {
326         struct {
327             /** target_hi_ro : RO; bitpos: [19:0]; default: 0;
328              *  actual target value value high 20 bits
329              */
330             uint32_t target_hi_ro: 20;
331             uint32_t reserved20: 12;
332         };
333         uint32_t val;
334     } hi;
335 } systimer_real_target_reg_t;
336 
337 
338 /** Group: VERSION REGISTER */
339 /** Type of date register
340  *  system timer version control register
341  */
342 typedef union {
343     struct {
344         /** date : R/W; bitpos: [31:0]; default: 35655795;
345          *  systimer register version
346          */
347         uint32_t date: 32;
348     };
349     uint32_t val;
350 } systimer_date_reg_t;
351 
352 
353 typedef struct systimer_dev_t {
354     volatile systimer_conf_reg_t conf;
355     volatile systimer_unit_op_reg_t unit_op[2];
356     volatile systimer_unit_load_val_reg_t unit_load_val[2];
357     volatile systimer_target_val_reg_t target_val[3];
358     volatile systimer_target_conf_reg_t target_conf[3];
359     volatile systimer_unit_value_reg_t unit_val[2];
360     volatile systimer_comp_load_reg_t comp_load[3];
361     volatile systimer_unit_load_reg_t unit_load[2];
362     volatile systimer_int_ena_reg_t int_ena;
363     volatile systimer_int_raw_reg_t int_raw;
364     volatile systimer_int_clr_reg_t int_clr;
365     volatile systimer_int_st_reg_t int_st;
366     volatile systimer_real_target_reg_t real_target[3];
367     uint32_t reserved_08c[28];
368     volatile systimer_date_reg_t date;
369 } systimer_dev_t;
370 
371 extern systimer_dev_t SYSTIMER;
372 
373 #ifndef __cplusplus
374 _Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
375 #endif
376 
377 #ifdef __cplusplus
378 }
379 #endif
380