1 /* 2 * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_SYSCON_REG_H_ 7 #define _SOC_SYSCON_REG_H_ 8 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #include "soc.h" 14 15 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0) 16 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ 17 /*description: reg_rst_tick_cnt.*/ 18 #define SYSCON_RST_TICK_CNT (BIT(12)) 19 #define SYSCON_RST_TICK_CNT_M (BIT(12)) 20 #define SYSCON_RST_TICK_CNT_V 0x1 21 #define SYSCON_RST_TICK_CNT_S 12 22 /* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 23 /*description: reg_clk_en.*/ 24 #define SYSCON_CLK_EN (BIT(11)) 25 #define SYSCON_CLK_EN_M (BIT(11)) 26 #define SYSCON_CLK_EN_V 0x1 27 #define SYSCON_CLK_EN_S 11 28 /* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 29 /*description: reg_clk_320m_en.*/ 30 #define SYSCON_CLK_320M_EN (BIT(10)) 31 #define SYSCON_CLK_320M_EN_M (BIT(10)) 32 #define SYSCON_CLK_320M_EN_V 0x1 33 #define SYSCON_CLK_320M_EN_S 10 34 /* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 35 /*description: reg_pre_div_cnt.*/ 36 #define SYSCON_PRE_DIV_CNT 0x000003FF 37 #define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) 38 #define SYSCON_PRE_DIV_CNT_V 0x3FF 39 #define SYSCON_PRE_DIV_CNT_S 0 40 41 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4) 42 /* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ 43 /*description: reg_tick_enable.*/ 44 #define SYSCON_TICK_ENABLE (BIT(16)) 45 #define SYSCON_TICK_ENABLE_M (BIT(16)) 46 #define SYSCON_TICK_ENABLE_V 0x1 47 #define SYSCON_TICK_ENABLE_S 16 48 /* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ 49 /*description: reg_ck8m_tick_num.*/ 50 #define SYSCON_CK8M_TICK_NUM 0x000000FF 51 #define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) 52 #define SYSCON_CK8M_TICK_NUM_V 0xFF 53 #define SYSCON_CK8M_TICK_NUM_S 8 54 /* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ 55 /*description: reg_xtal_tick_num.*/ 56 #define SYSCON_XTAL_TICK_NUM 0x000000FF 57 #define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) 58 #define SYSCON_XTAL_TICK_NUM_V 0xFF 59 #define SYSCON_XTAL_TICK_NUM_S 0 60 61 #define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8) 62 /* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 63 /*description: reg_clk_xtal_oen.*/ 64 #define SYSCON_CLK_XTAL_OEN (BIT(10)) 65 #define SYSCON_CLK_XTAL_OEN_M (BIT(10)) 66 #define SYSCON_CLK_XTAL_OEN_V 0x1 67 #define SYSCON_CLK_XTAL_OEN_S 10 68 /* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 69 /*description: reg_clk40x_bb_oen.*/ 70 #define SYSCON_CLK40X_BB_OEN (BIT(9)) 71 #define SYSCON_CLK40X_BB_OEN_M (BIT(9)) 72 #define SYSCON_CLK40X_BB_OEN_V 0x1 73 #define SYSCON_CLK40X_BB_OEN_S 9 74 /* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ 75 /*description: reg_clk_dac_cpu_oen.*/ 76 #define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) 77 #define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) 78 #define SYSCON_CLK_DAC_CPU_OEN_V 0x1 79 #define SYSCON_CLK_DAC_CPU_OEN_S 8 80 /* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 81 /*description: reg_clk_adc_inf_oen.*/ 82 #define SYSCON_CLK_ADC_INF_OEN (BIT(7)) 83 #define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) 84 #define SYSCON_CLK_ADC_INF_OEN_V 0x1 85 #define SYSCON_CLK_ADC_INF_OEN_S 7 86 /* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 87 /*description: reg_clk_320m_oen.*/ 88 #define SYSCON_CLK_320M_OEN (BIT(6)) 89 #define SYSCON_CLK_320M_OEN_M (BIT(6)) 90 #define SYSCON_CLK_320M_OEN_V 0x1 91 #define SYSCON_CLK_320M_OEN_S 6 92 /* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 93 /*description: reg_clk160_oen.*/ 94 #define SYSCON_CLK160_OEN (BIT(5)) 95 #define SYSCON_CLK160_OEN_M (BIT(5)) 96 #define SYSCON_CLK160_OEN_V 0x1 97 #define SYSCON_CLK160_OEN_S 5 98 /* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ 99 /*description: reg_clk80_oen.*/ 100 #define SYSCON_CLK80_OEN (BIT(4)) 101 #define SYSCON_CLK80_OEN_M (BIT(4)) 102 #define SYSCON_CLK80_OEN_V 0x1 103 #define SYSCON_CLK80_OEN_S 4 104 /* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 105 /*description: reg_clk_bb_oen.*/ 106 #define SYSCON_CLK_BB_OEN (BIT(3)) 107 #define SYSCON_CLK_BB_OEN_M (BIT(3)) 108 #define SYSCON_CLK_BB_OEN_V 0x1 109 #define SYSCON_CLK_BB_OEN_S 3 110 /* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 111 /*description: reg_clk44_oen.*/ 112 #define SYSCON_CLK44_OEN (BIT(2)) 113 #define SYSCON_CLK44_OEN_M (BIT(2)) 114 #define SYSCON_CLK44_OEN_V 0x1 115 #define SYSCON_CLK44_OEN_S 2 116 /* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 117 /*description: reg_clk22_oen.*/ 118 #define SYSCON_CLK22_OEN (BIT(1)) 119 #define SYSCON_CLK22_OEN_M (BIT(1)) 120 #define SYSCON_CLK22_OEN_V 0x1 121 #define SYSCON_CLK22_OEN_S 1 122 /* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 123 /*description: reg_clk20_oen.*/ 124 #define SYSCON_CLK20_OEN (BIT(0)) 125 #define SYSCON_CLK20_OEN_M (BIT(0)) 126 #define SYSCON_CLK20_OEN_V 0x1 127 #define SYSCON_CLK20_OEN_S 0 128 129 #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC) 130 /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 131 /*description: reg_wifi_bb_cfg.*/ 132 #define SYSCON_WIFI_BB_CFG 0xFFFFFFFF 133 #define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) 134 #define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF 135 #define SYSCON_WIFI_BB_CFG_S 0 136 137 #define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10) 138 /* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 139 /*description: reg_wifi_bb_cfg_2.*/ 140 #define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF 141 #define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) 142 #define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF 143 #define SYSCON_WIFI_BB_CFG_2_S 0 144 145 #define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14) 146 /* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 147 /*description: reg_wifi_clk_en.*/ 148 #define SYSCON_WIFI_CLK_EN 0xFFFFFFFF 149 #define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) 150 #define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF 151 #define SYSCON_WIFI_CLK_EN_S 0 152 153 #define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18) 154 /* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 155 /*description: reg_wifi_rst.*/ 156 #define SYSCON_WIFI_RST 0xFFFFFFFF 157 #define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) 158 #define SYSCON_WIFI_RST_V 0xFFFFFFFF 159 #define SYSCON_WIFI_RST_S 0 160 161 #define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG 162 /* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 163 /*description: */ 164 #define SYSTEM_WIFI_CLK_EN 0x00FB9FCF 165 #define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S)) 166 #define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF 167 #define SYSTEM_WIFI_CLK_EN_S 0 168 169 /* Mask for all Wifi clock bits, 6 */ 170 #define SYSTEM_WIFI_CLK_WIFI_EN 0x0 171 #define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S)) 172 #define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 173 #define SYSTEM_WIFI_CLK_WIFI_EN_S 0 174 /* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */ 175 #define SYSTEM_WIFI_CLK_BT_EN 0x0 176 #define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S)) 177 #define SYSTEM_WIFI_CLK_BT_EN_V 0x0 178 #define SYSTEM_WIFI_CLK_BT_EN_S 0 179 /* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */ 180 #define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F 181 182 /* Digital team to check */ 183 //bluetooth baseband bit11 184 #define SYSTEM_BT_BASEBAND_EN BIT(11) 185 //bluetooth LC bit16 and bit17 186 #define SYSTEM_BT_LC_EN (BIT(16)|BIT(17)) 187 188 /* Remaining single bit clock masks */ 189 #define SYSTEM_WIFI_CLK_SDIOSLAVE_EN BIT(4) 190 #define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5) 191 #define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12) 192 #define SYSTEM_WIFI_CLK_EMAC_EN BIT(14) 193 #define SYSTEM_WIFI_CLK_RNG_EN BIT(15) 194 195 #define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG 196 #define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG 197 /* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 198 /*description: */ 199 #define SYSTEM_BB_RST BIT(0) 200 #define SYSTEM_FE_RST BIT(1) 201 #define SYSTEM_MAC_RST BIT(2) 202 #define SYSTEM_BT_RST BIT(3) 203 #define SYSTEM_BTMAC_RST BIT(4) 204 #define SYSTEM_SDIO_RST BIT(5) 205 #define SYSTEM_EMAC_RST BIT(7) 206 #define SYSTEM_MACPWR_RST BIT(8) 207 #define SYSTEM_RW_BTMAC_RST BIT(9) 208 #define SYSTEM_RW_BTLP_RST BIT(10) 209 #define BLE_REG_REST_BIT BIT(11) 210 #define BLE_PWR_REG_REST_BIT BIT(12) 211 #define BLE_BB_REG_REST_BIT BIT(13) 212 #define BLE_RPA_REST_BIT BIT(27) 213 214 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C) 215 /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 216 /*description: reg_peri_io_swap.*/ 217 #define SYSCON_PERI_IO_SWAP 0x000000FF 218 #define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) 219 #define SYSCON_PERI_IO_SWAP_V 0xFF 220 #define SYSCON_PERI_IO_SWAP_S 0 221 222 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20) 223 /* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 224 /*description: reg_ext_mem_pms_lock.*/ 225 #define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) 226 #define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) 227 #define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 228 #define SYSCON_EXT_MEM_PMS_LOCK_S 0 229 230 #define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28) 231 /* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 232 /*description: reg_flash_ace0_attr.*/ 233 #define SYSCON_FLASH_ACE0_ATTR 0x00000003 234 #define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) 235 #define SYSCON_FLASH_ACE0_ATTR_V 0x3 236 #define SYSCON_FLASH_ACE0_ATTR_S 0 237 238 #define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C) 239 /* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 240 /*description: reg_flash_ace1_attr.*/ 241 #define SYSCON_FLASH_ACE1_ATTR 0x00000003 242 #define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) 243 #define SYSCON_FLASH_ACE1_ATTR_V 0x3 244 #define SYSCON_FLASH_ACE1_ATTR_S 0 245 246 #define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30) 247 /* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 248 /*description: reg_flash_ace2_attr.*/ 249 #define SYSCON_FLASH_ACE2_ATTR 0x00000003 250 #define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) 251 #define SYSCON_FLASH_ACE2_ATTR_V 0x3 252 #define SYSCON_FLASH_ACE2_ATTR_S 0 253 254 #define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34) 255 /* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 256 /*description: reg_flash_ace3_attr.*/ 257 #define SYSCON_FLASH_ACE3_ATTR 0x00000003 258 #define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) 259 #define SYSCON_FLASH_ACE3_ATTR_V 0x3 260 #define SYSCON_FLASH_ACE3_ATTR_S 0 261 262 #define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38) 263 /* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 264 /*description: reg_flash_ace0_addr_s.*/ 265 #define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF 266 #define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) 267 #define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF 268 #define SYSCON_FLASH_ACE0_ADDR_S_S 0 269 270 #define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C) 271 /* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */ 272 /*description: reg_flash_ace1_addr_s.*/ 273 #define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF 274 #define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) 275 #define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF 276 #define SYSCON_FLASH_ACE1_ADDR_S_S 0 277 278 #define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40) 279 /* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */ 280 /*description: reg_flash_ace2_addr_s.*/ 281 #define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF 282 #define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) 283 #define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF 284 #define SYSCON_FLASH_ACE2_ADDR_S_S 0 285 286 #define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44) 287 /* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */ 288 /*description: reg_flash_ace3_addr_s.*/ 289 #define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF 290 #define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) 291 #define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF 292 #define SYSCON_FLASH_ACE3_ADDR_S_S 0 293 294 #define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48) 295 /* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 296 /*description: reg_flash_ace0_size.*/ 297 #define SYSCON_FLASH_ACE0_SIZE 0x00001FFF 298 #define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) 299 #define SYSCON_FLASH_ACE0_SIZE_V 0x1FFF 300 #define SYSCON_FLASH_ACE0_SIZE_S 0 301 302 #define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C) 303 /* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 304 /*description: reg_flash_ace1_size.*/ 305 #define SYSCON_FLASH_ACE1_SIZE 0x00001FFF 306 #define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) 307 #define SYSCON_FLASH_ACE1_SIZE_V 0x1FFF 308 #define SYSCON_FLASH_ACE1_SIZE_S 0 309 310 #define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50) 311 /* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 312 /*description: reg_flash_ace2_size.*/ 313 #define SYSCON_FLASH_ACE2_SIZE 0x00001FFF 314 #define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) 315 #define SYSCON_FLASH_ACE2_SIZE_V 0x1FFF 316 #define SYSCON_FLASH_ACE2_SIZE_S 0 317 318 #define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54) 319 /* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 320 /*description: reg_flash_ace3_size.*/ 321 #define SYSCON_FLASH_ACE3_SIZE 0x00001FFF 322 #define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) 323 #define SYSCON_FLASH_ACE3_SIZE_V 0x1FFF 324 #define SYSCON_FLASH_ACE3_SIZE_S 0 325 326 #define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88) 327 /* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ 328 /*description: reg_spi_mem_reject_cde.*/ 329 #define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F 330 #define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) 331 #define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F 332 #define SYSCON_SPI_MEM_REJECT_CDE_S 2 333 /* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 334 /*description: reg_spi_mem_reject_clr.*/ 335 #define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) 336 #define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) 337 #define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 338 #define SYSCON_SPI_MEM_REJECT_CLR_S 1 339 /* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ 340 /*description: reg_spi_mem_reject_int.*/ 341 #define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) 342 #define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) 343 #define SYSCON_SPI_MEM_REJECT_INT_V 0x1 344 #define SYSCON_SPI_MEM_REJECT_INT_S 0 345 346 #define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C) 347 /* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 348 /*description: reg_spi_mem_reject_addr.*/ 349 #define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF 350 #define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) 351 #define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF 352 #define SYSCON_SPI_MEM_REJECT_ADDR_S 0 353 354 #define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90) 355 /* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 356 /*description: reg_sdio_win_access_en.*/ 357 #define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) 358 #define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) 359 #define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 360 #define SYSCON_SDIO_WIN_ACCESS_EN_S 0 361 362 #define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94) 363 /* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 364 /*description: reg_redcy_andor.*/ 365 #define SYSCON_REDCY_ANDOR (BIT(31)) 366 #define SYSCON_REDCY_ANDOR_M (BIT(31)) 367 #define SYSCON_REDCY_ANDOR_V 0x1 368 #define SYSCON_REDCY_ANDOR_S 31 369 /* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 370 /*description: reg_redcy_sig0.*/ 371 #define SYSCON_REDCY_SIG0 0x7FFFFFFF 372 #define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) 373 #define SYSCON_REDCY_SIG0_V 0x7FFFFFFF 374 #define SYSCON_REDCY_SIG0_S 0 375 376 #define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98) 377 /* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 378 /*description: reg_redcy_nandor.*/ 379 #define SYSCON_REDCY_NANDOR (BIT(31)) 380 #define SYSCON_REDCY_NANDOR_M (BIT(31)) 381 #define SYSCON_REDCY_NANDOR_V 0x1 382 #define SYSCON_REDCY_NANDOR_S 31 383 /* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 384 /*description: reg_redcy_sig1.*/ 385 #define SYSCON_REDCY_SIG1 0x7FFFFFFF 386 #define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) 387 #define SYSCON_REDCY_SIG1_V 0x7FFFFFFF 388 #define SYSCON_REDCY_SIG1_S 0 389 390 #define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C) 391 /* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 392 /*description: reg_freq_mem_force_pd.*/ 393 #define SYSCON_FREQ_MEM_FORCE_PD (BIT(7)) 394 #define SYSCON_FREQ_MEM_FORCE_PD_M (BIT(7)) 395 #define SYSCON_FREQ_MEM_FORCE_PD_V 0x1 396 #define SYSCON_FREQ_MEM_FORCE_PD_S 7 397 /* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */ 398 /*description: reg_freq_mem_force_pu.*/ 399 #define SYSCON_FREQ_MEM_FORCE_PU (BIT(6)) 400 #define SYSCON_FREQ_MEM_FORCE_PU_M (BIT(6)) 401 #define SYSCON_FREQ_MEM_FORCE_PU_V 0x1 402 #define SYSCON_FREQ_MEM_FORCE_PU_S 6 403 /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 404 /*description: reg_dc_mem_force_pd.*/ 405 #define SYSCON_DC_MEM_FORCE_PD (BIT(5)) 406 #define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) 407 #define SYSCON_DC_MEM_FORCE_PD_V 0x1 408 #define SYSCON_DC_MEM_FORCE_PD_S 5 409 /* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 410 /*description: reg_dc_mem_force_pu.*/ 411 #define SYSCON_DC_MEM_FORCE_PU (BIT(4)) 412 #define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) 413 #define SYSCON_DC_MEM_FORCE_PU_V 0x1 414 #define SYSCON_DC_MEM_FORCE_PU_S 4 415 /* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 416 /*description: reg_pbus_mem_force_pd.*/ 417 #define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) 418 #define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) 419 #define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 420 #define SYSCON_PBUS_MEM_FORCE_PD_S 3 421 /* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 422 /*description: reg_pbus_mem_force_pu.*/ 423 #define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) 424 #define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) 425 #define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 426 #define SYSCON_PBUS_MEM_FORCE_PU_S 2 427 /* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 428 /*description: reg_agc_mem_force_pd.*/ 429 #define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) 430 #define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) 431 #define SYSCON_AGC_MEM_FORCE_PD_V 0x1 432 #define SYSCON_AGC_MEM_FORCE_PD_S 1 433 /* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ 434 /*description: reg_agc_mem_force_pu.*/ 435 #define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) 436 #define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) 437 #define SYSCON_AGC_MEM_FORCE_PU_V 0x1 438 #define SYSCON_AGC_MEM_FORCE_PU_S 0 439 440 #define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0) 441 /* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 442 /*description: reg_nobypass_cpu_iso_rst.*/ 443 #define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) 444 #define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) 445 #define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 446 #define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 447 /* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 448 /*description: reg_retention_link_addr.*/ 449 #define SYSCON_RETENTION_LINK_ADDR 0x07FFFFFF 450 #define SYSCON_RETENTION_LINK_ADDR_M ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S)) 451 #define SYSCON_RETENTION_LINK_ADDR_V 0x7FFFFFF 452 #define SYSCON_RETENTION_LINK_ADDR_S 0 453 454 #define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA4) 455 /* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */ 456 /*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t 457 hen only when have access the sram have clock.*/ 458 #define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000F 459 #define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S)) 460 #define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0xF 461 #define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3 462 /* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ 463 /*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th 464 en only when have access the rom have clock.*/ 465 #define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007 466 #define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S)) 467 #define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7 468 #define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 469 470 #define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xA8) 471 /* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */ 472 /*description: Set 1 to let sram power down.*/ 473 #define SYSCON_SRAM_POWER_DOWN 0x0000000F 474 #define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S)) 475 #define SYSCON_SRAM_POWER_DOWN_V 0xF 476 #define SYSCON_SRAM_POWER_DOWN_S 3 477 /* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ 478 /*description: Set 1 to let rom power down.*/ 479 #define SYSCON_ROM_POWER_DOWN 0x00000007 480 #define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S)) 481 #define SYSCON_ROM_POWER_DOWN_V 0x7 482 #define SYSCON_ROM_POWER_DOWN_S 0 483 484 #define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xAC) 485 /* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */ 486 /*description: Set 1 to let sram power up.*/ 487 #define SYSCON_SRAM_POWER_UP 0x0000000F 488 #define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S)) 489 #define SYSCON_SRAM_POWER_UP_V 0xF 490 #define SYSCON_SRAM_POWER_UP_S 3 491 /* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ 492 /*description: Set 1 to let rom power up.*/ 493 #define SYSCON_ROM_POWER_UP 0x00000007 494 #define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S)) 495 #define SYSCON_ROM_POWER_UP_V 0x7 496 #define SYSCON_ROM_POWER_UP_S 0 497 498 #define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0xB0) 499 /* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 500 /*description: reg_rnd_data.*/ 501 #define SYSCON_RND_DATA 0xFFFFFFFF 502 #define SYSCON_RND_DATA_M ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S)) 503 #define SYSCON_RND_DATA_V 0xFFFFFFFF 504 #define SYSCON_RND_DATA_S 0 505 506 #define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xB4) 507 /* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ 508 /*description: reg_peri_backup_ena.*/ 509 #define SYSCON_PERI_BACKUP_ENA (BIT(31)) 510 #define SYSCON_PERI_BACKUP_ENA_M (BIT(31)) 511 #define SYSCON_PERI_BACKUP_ENA_V 0x1 512 #define SYSCON_PERI_BACKUP_ENA_S 31 513 /* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */ 514 /*description: reg_peri_backup_to_mem.*/ 515 #define SYSCON_PERI_BACKUP_TO_MEM (BIT(30)) 516 #define SYSCON_PERI_BACKUP_TO_MEM_M (BIT(30)) 517 #define SYSCON_PERI_BACKUP_TO_MEM_V 0x1 518 #define SYSCON_PERI_BACKUP_TO_MEM_S 30 519 /* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */ 520 /*description: reg_peri_backup_start.*/ 521 #define SYSCON_PERI_BACKUP_START (BIT(29)) 522 #define SYSCON_PERI_BACKUP_START_M (BIT(29)) 523 #define SYSCON_PERI_BACKUP_START_V 0x1 524 #define SYSCON_PERI_BACKUP_START_S 29 525 /* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */ 526 /*description: reg_peri_backup_size.*/ 527 #define SYSCON_PERI_BACKUP_SIZE 0x000003FF 528 #define SYSCON_PERI_BACKUP_SIZE_M ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S)) 529 #define SYSCON_PERI_BACKUP_SIZE_V 0x3FF 530 #define SYSCON_PERI_BACKUP_SIZE_S 19 531 /* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */ 532 /*description: reg_peri_backup_tout_thres.*/ 533 #define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FF 534 #define SYSCON_PERI_BACKUP_TOUT_THRES_M ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S)) 535 #define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x3FF 536 #define SYSCON_PERI_BACKUP_TOUT_THRES_S 9 537 /* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */ 538 /*description: reg_peri_backup_burst_limit.*/ 539 #define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001F 540 #define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S)) 541 #define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F 542 #define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4 543 /* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */ 544 /*description: reg_peri_backup_flow_err.*/ 545 #define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003 546 #define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S)) 547 #define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3 548 #define SYSCON_PERI_BACKUP_FLOW_ERR_S 1 549 550 #define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xB8) 551 /* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 552 /*description: reg_backup_apb_start_addr.*/ 553 #define SYSCON_BACKUP_APB_START_ADDR 0xFFFFFFFF 554 #define SYSCON_BACKUP_APB_START_ADDR_M ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S)) 555 #define SYSCON_BACKUP_APB_START_ADDR_V 0xFFFFFFFF 556 #define SYSCON_BACKUP_APB_START_ADDR_S 0 557 558 #define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0xBC) 559 /* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 560 /*description: reg_backup_mem_start_addr.*/ 561 #define SYSCON_BACKUP_MEM_START_ADDR 0xFFFFFFFF 562 #define SYSCON_BACKUP_MEM_START_ADDR_M ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S)) 563 #define SYSCON_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF 564 #define SYSCON_BACKUP_MEM_START_ADDR_S 0 565 566 #define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0xC0) 567 /* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ 568 /*description: reg_peri_backup_err_int_raw.*/ 569 #define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1)) 570 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (BIT(1)) 571 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x1 572 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1 573 /* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */ 574 /*description: reg_peri_backup_done_int_raw.*/ 575 #define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0)) 576 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (BIT(0)) 577 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1 578 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0 579 580 #define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0xC4) 581 /* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ 582 /*description: reg_peri_backup_err_int_st.*/ 583 #define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1)) 584 #define SYSCON_PERI_BACKUP_ERR_INT_ST_M (BIT(1)) 585 #define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x1 586 #define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1 587 /* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */ 588 /*description: reg_peri_backup_done_int_st.*/ 589 #define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0)) 590 #define SYSCON_PERI_BACKUP_DONE_INT_ST_M (BIT(0)) 591 #define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1 592 #define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0 593 594 #define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xC8) 595 /* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ 596 /*description: reg_peri_backup_err_int_ena.*/ 597 #define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1)) 598 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (BIT(1)) 599 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x1 600 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1 601 /* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */ 602 /*description: reg_peri_backup_done_int_ena.*/ 603 #define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0)) 604 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (BIT(0)) 605 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1 606 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0 607 608 #define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0xD0) 609 /* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ 610 /*description: reg_peri_backup_err_int_clr.*/ 611 #define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1)) 612 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (BIT(1)) 613 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x1 614 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1 615 /* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */ 616 /*description: reg_peri_backup_done_int_clr.*/ 617 #define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0)) 618 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (BIT(0)) 619 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1 620 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0 621 622 #define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) 623 /* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */ 624 /*description: reg_dateVersion control.*/ 625 #define SYSCON_DATE 0xFFFFFFFF 626 #define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) 627 #define SYSCON_DATE_V 0xFFFFFFFF 628 #define SYSCON_DATE_S 0 629 630 631 #ifdef __cplusplus 632 } 633 #endif 634 635 636 637 #endif /*_SOC_SYSCON_REG_H_ */ 638
