1 /*
2 * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <sys/param.h>
8 #include "sdkconfig.h"
9 #include "soc/soc_caps.h"
10 #include "hal/adc_hal_common.h"
11 #include "hal/adc_ll.h"
12 #include "hal/assert.h"
13
14 /*---------------------------------------------------------------
15 Controller Setting
16 ---------------------------------------------------------------*/
17 #pragma GCC diagnostic push
18 #pragma GCC diagnostic ignored "-Wreturn-type"
get_controller(adc_unit_t unit,adc_hal_work_mode_t work_mode)19 static adc_ll_controller_t get_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
20 {
21 if (unit == ADC_UNIT_1) {
22 switch (work_mode) {
23 #if SOC_ULP_HAS_ADC
24 case ADC_HAL_ULP_FSM_MODE:
25 return ADC_LL_CTRL_ULP;
26 #endif
27 case ADC_HAL_SINGLE_READ_MODE:
28 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
29 return ADC_LL_CTRL_DIG;
30 #elif SOC_ADC_RTC_CTRL_SUPPORTED
31 return ADC_LL_CTRL_RTC;
32 #endif
33 case ADC_HAL_CONTINUOUS_READ_MODE:
34 return ADC_LL_CTRL_DIG;
35 default:
36 abort();
37 }
38 } else {
39 switch (work_mode) {
40 #if SOC_ULP_HAS_ADC
41 case ADC_HAL_ULP_FSM_MODE:
42 return ADC_LL_CTRL_ULP;
43 #endif
44 #if !SOC_ADC_ARBITER_SUPPORTED //No ADC2 arbiter on ESP32
45 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
46 default:
47 return ADC_LL_CTRL_DIG;
48 #else
49 case ADC_HAL_SINGLE_READ_MODE:
50 return ADC_LL_CTRL_RTC;
51 case ADC_HAL_CONTINUOUS_READ_MODE:
52 return ADC_LL_CTRL_DIG;
53 case ADC_HAL_PWDET_MODE:
54 return ADC_LL_CTRL_PWDET;
55 default:
56 abort();
57 #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
58 #else
59 default:
60 return ADC_LL_CTRL_ARB;
61 #endif
62 }
63 }
64 }
65 #pragma GCC diagnostic pop
66
adc_hal_set_controller(adc_unit_t unit,adc_hal_work_mode_t work_mode)67 void adc_hal_set_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
68 {
69 adc_ll_controller_t ctrlr = get_controller(unit, work_mode);
70 adc_ll_set_controller(unit, ctrlr);
71 }
72
73
74 /*---------------------------------------------------------------
75 Arbiter
76 ---------------------------------------------------------------*/
77 #if SOC_ADC_ARBITER_SUPPORTED
adc_hal_arbiter_config(adc_arbiter_t * config)78 void adc_hal_arbiter_config(adc_arbiter_t *config)
79 {
80 adc_ll_set_arbiter_work_mode(config->mode);
81 adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
82 }
83 #endif // #if SOC_ADC_ARBITER_SUPPORTED
84
85
86 /*---------------------------------------------------------------
87 ADC calibration setting
88 ---------------------------------------------------------------*/
89 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
90 //For chips without RTC controller, Digital controller is used to trigger an ADC single read.
91 #include "esp_rom_sys.h"
92
adc_hal_calibration_init(adc_unit_t adc_n)93 void adc_hal_calibration_init(adc_unit_t adc_n)
94 {
95 adc_ll_calibration_init(adc_n);
96 }
97
98 static uint32_t s_previous_init_code[SOC_ADC_PERIPH_NUM] = {
99 [0 ... (SOC_ADC_PERIPH_NUM - 1)] = -1,
100 };
101
adc_hal_set_calibration_param(adc_unit_t adc_n,uint32_t param)102 void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param)
103 {
104 if (param != s_previous_init_code[adc_n]) {
105 adc_ll_set_calibration_param(adc_n, param);
106 s_previous_init_code[adc_n] = param;
107 }
108 }
109
110 #if SOC_ADC_SELF_HW_CALI_SUPPORTED
cal_setup(adc_unit_t adc_n,adc_atten_t atten)111 static void cal_setup(adc_unit_t adc_n, adc_atten_t atten)
112 {
113 adc_hal_set_controller(adc_n, ADC_HAL_SINGLE_READ_MODE);
114 adc_oneshot_ll_disable_all_unit();
115 // Enableinternal connect GND (for calibration).
116 adc_oneshot_ll_disable_channel(adc_n);
117 /**
118 * Note:
119 * When controlled by RTC controller, when all channels are disabled, HW auto selects channel0 atten param.
120 * When controlled by DIG controller, unit and channel are not related to attenuation
121 */
122 adc_oneshot_ll_set_atten(adc_n, 0, atten);
123 adc_oneshot_ll_enable(adc_n);
124 }
125
read_cal_channel(adc_unit_t adc_n)126 static uint32_t read_cal_channel(adc_unit_t adc_n)
127 {
128 uint32_t event = (adc_n == ADC_UNIT_1) ? ADC_LL_EVENT_ADC1_ONESHOT_DONE : ADC_LL_EVENT_ADC2_ONESHOT_DONE;
129 adc_oneshot_ll_clear_event(event);
130
131 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
132 adc_oneshot_ll_start(false);
133 esp_rom_delay_us(5);
134 adc_oneshot_ll_start(true);
135 #else
136 adc_oneshot_ll_start(adc_n);
137 #endif
138
139 while(!adc_oneshot_ll_get_event(event));
140
141 uint32_t read_val = -1;
142 read_val = adc_oneshot_ll_get_raw_result(adc_n);
143 if (adc_oneshot_ll_raw_check_valid(adc_n, read_val) == false) {
144 return -1;
145 }
146 return read_val;
147 }
148
149 #define ADC_HAL_CAL_TIMES (10)
150 #define ADC_HAL_CAL_OFFSET_RANGE (4096)
151
adc_hal_self_calibration(adc_unit_t adc_n,adc_atten_t atten,bool internal_gnd)152 uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool internal_gnd)
153 {
154 #if SOC_ADC_ARBITER_SUPPORTED
155 if (adc_n == ADC_UNIT_2) {
156 adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
157 adc_hal_arbiter_config(&config);
158 }
159 #endif // #if SOC_ADC_ARBITER_SUPPORTED
160
161 cal_setup(adc_n, atten);
162
163 adc_ll_calibration_prepare(adc_n, internal_gnd);
164
165 uint32_t code_list[ADC_HAL_CAL_TIMES] = {0};
166 uint32_t code_sum = 0;
167 uint32_t code_h = 0;
168 uint32_t code_l = 0;
169 uint32_t chk_code = 0;
170
171 for (uint8_t rpt = 0 ; rpt < ADC_HAL_CAL_TIMES ; rpt ++) {
172 code_h = ADC_HAL_CAL_OFFSET_RANGE;
173 code_l = 0;
174 chk_code = (code_h + code_l) / 2;
175 adc_ll_set_calibration_param(adc_n, chk_code);
176 uint32_t self_cal = read_cal_channel(adc_n);
177 while (code_h - code_l > 1) {
178 if (self_cal == 0) {
179 code_h = chk_code;
180 } else {
181 code_l = chk_code;
182 }
183 chk_code = (code_h + code_l) / 2;
184 adc_ll_set_calibration_param(adc_n, chk_code);
185 self_cal = read_cal_channel(adc_n);
186 if ((code_h - code_l == 1)) {
187 chk_code += 1;
188 adc_ll_set_calibration_param(adc_n, chk_code);
189 self_cal = read_cal_channel(adc_n);
190 }
191 }
192 code_list[rpt] = chk_code;
193 code_sum += chk_code;
194 }
195
196 code_l = code_list[0];
197 code_h = code_list[0];
198 for (uint8_t i = 0 ; i < ADC_HAL_CAL_TIMES ; i++) {
199 code_l = MIN(code_l, code_list[i]);
200 code_h = MAX(code_h, code_list[i]);
201 }
202
203 chk_code = code_h + code_l;
204 uint32_t ret = ((code_sum - chk_code) % (ADC_HAL_CAL_TIMES - 2) < 4)
205 ? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
206 : (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
207
208 adc_ll_calibration_finish(adc_n);
209 return ret;
210 }
211 #endif //#if SOC_ADC_SELF_HW_CALI_SUPPORTED
212 #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
213
