1 /*
2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #pragma once
8
9 #include <stdbool.h>
10 #include <stdint.h>
11 #include <stddef.h>
12 #include "esp_assert.h"
13 #include "soc/rtc_cntl_reg.h"
14 #include "soc/reset_reasons.h"
15
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19
20 /** \defgroup rtc_apis, rtc registers and memory related apis
21 * @brief rtc apis
22 */
23
24 /** @addtogroup rtc_apis
25 * @{
26 */
27
28 /**************************************************************************************
29 * Note: *
30 * Some Rtc memory and registers are used, in ROM or in internal library. *
31 * Please do not use reserved or used rtc memory or registers. *
32 * *
33 *************************************************************************************
34 * RTC Memory & Store Register usage
35 *************************************************************************************
36 * rtc memory addr type size usage
37 * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
38 * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
39 *
40 * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
41 *
42 *************************************************************************************
43 * RTC store registers usage
44 * RTC_CNTL_STORE0_REG Reserved
45 * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
46 * RTC_CNTL_STORE2_REG Boot time, low word
47 * RTC_CNTL_STORE3_REG Boot time, high word
48 * RTC_CNTL_STORE4_REG External XTAL frequency
49 * RTC_CNTL_STORE5_REG FAST_RTC_MEMORY_LENGTH
50 * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
51 * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
52 *************************************************************************************
53 */
54
55 #define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
56 #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
57 #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
58 #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
59 #define RTC_ENTRY_LENGTH_REG RTC_CNTL_STORE5_REG
60 #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
61 #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
62 #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
63
64 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
65
66 typedef enum {
67 AWAKE = 0, //<CPU ON
68 LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
69 DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
70 } SLEEP_MODE;
71
72 typedef enum {
73 NO_MEAN = 0,
74 POWERON_RESET = 1, /**<1, Vbat power on reset*/
75 RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
76 DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
77 TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
78 TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
79 RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
80 INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
81 TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
82 RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
83 RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
84 RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
85 RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
86 TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
87 SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
88 GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
89 EFUSE_RESET = 20, /**<20, efuse reset digital core*/
90 USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
91 USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
92 POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
93 } RESET_REASON;
94
95 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
96 ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
97 ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
98 ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
99 ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
100 ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
101 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
102 ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
103 ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
104 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
105 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
106 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
107 ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
108 ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
109 ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
110 ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
111 ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
112 ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
113 ESP_STATIC_ASSERT((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
114
115 typedef enum {
116 NO_SLEEP = 0,
117 EXT_EVENT0_TRIG = BIT0,
118 EXT_EVENT1_TRIG = BIT1,
119 GPIO_TRIG = BIT2,
120 TIMER_EXPIRE = BIT3,
121 SDIO_TRIG = BIT4,
122 MAC_TRIG = BIT5,
123 UART0_TRIG = BIT6,
124 UART1_TRIG = BIT7,
125 TOUCH_TRIG = BIT8,
126 SAR_TRIG = BIT9,
127 BT_TRIG = BIT10,
128 RISCV_TRIG = BIT11,
129 XTAL_DEAD_TRIG = BIT12,
130 RISCV_TRAP_TRIG = BIT13,
131 USB_TRIG = BIT14
132 } WAKEUP_REASON;
133
134 typedef enum {
135 DISEN_WAKEUP = NO_SLEEP,
136 EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
137 EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
138 GPIO_TRIG_EN = GPIO_TRIG,
139 TIMER_EXPIRE_EN = TIMER_EXPIRE,
140 SDIO_TRIG_EN = SDIO_TRIG,
141 MAC_TRIG_EN = MAC_TRIG,
142 UART0_TRIG_EN = UART0_TRIG,
143 UART1_TRIG_EN = UART1_TRIG,
144 TOUCH_TRIG_EN = TOUCH_TRIG,
145 SAR_TRIG_EN = SAR_TRIG,
146 BT_TRIG_EN = BT_TRIG,
147 RISCV_TRIG_EN = RISCV_TRIG,
148 XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
149 RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
150 USB_TRIG_EN = USB_TRIG
151 } WAKEUP_ENABLE;
152
153 /**
154 * @brief Get the reset reason for CPU.
155 *
156 * @param int cpu_no : CPU no.
157 *
158 * @return RESET_REASON
159 */
160 RESET_REASON rtc_get_reset_reason(int cpu_no);
161
162 /**
163 * @brief Get the wakeup cause for CPU.
164 *
165 * @param int cpu_no : CPU no.
166 *
167 * @return WAKEUP_REASON
168 */
169 WAKEUP_REASON rtc_get_wakeup_cause(void);
170
171 typedef void (* esp_rom_wake_func_t)(void);
172
173 /**
174 * @brief Read stored RTC wake function address
175 *
176 * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
177 * valid means that both stored stub length and stored wake function address are four-byte aligned non-zero values
178 * and the crc check passes
179 *
180 * @param None
181 *
182 * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
183 */
184 esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
185
186 /**
187 * @brief Store new RTC wake function address
188 *
189 * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
190 * memory is calculated and stored also.
191 *
192 * @param entry_addr Address of function. should be 4-bytes aligned otherwise it will not start from the stub after wake from deepsleep，
193 * if NULL length will be ignored and all registers are cleared to 0.
194 *
195 * @param length length of function in RTC fast memory. should be less than RTC Fast memory size and aligned to 4-bytes.
196 * otherwise all registers are cleared to 0.
197 *
198 * @return None
199 */
200 void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
201
202 /**
203 * @brief Suppress ROM log by setting specific RTC control register.
204 * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
205 *
206 * @param None
207 *
208 * @return None
209 */
rtc_suppress_rom_log(void)210 static inline void rtc_suppress_rom_log(void)
211 {
212 /* To disable logging in the ROM, only the least significant bit of the register is used,
213 * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
214 * you need to write to this register in the same format.
215 * Namely, the upper 16 bits and lower should be the same.
216 */
217 REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
218 }
219
220 /**
221 * @brief Software Reset digital core.
222 *
223 * It is not recommended to use this function in esp-idf, use
224 * esp_restart() instead.
225 *
226 * @param None
227 *
228 * @return None
229 */
230 void software_reset(void);
231
232 /**
233 * @brief Software Reset digital core.
234 *
235 * It is not recommended to use this function in esp-idf, use
236 * esp_restart() instead.
237 *
238 * @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
239 *
240 * @return None
241 */
242 void software_reset_cpu(int cpu_no);
243
244 /**
245 * @}
246 */
247
248 #ifdef __cplusplus
249 }
250 #endif
251
