1 /*
2 * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <sys/param.h>
8 #include "sdkconfig.h"
9 #include "esp_log.h"
10 #include "assert.h"
11 #include "esp_efuse_utility.h"
12 #include "soc/efuse_periph.h"
13 #include "hal/efuse_hal.h"
14
15 static const char *TAG = "efuse";
16
17 #ifdef CONFIG_EFUSE_VIRTUAL
18 extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
19 #endif // CONFIG_EFUSE_VIRTUAL
20
21 /*Range addresses to read blocks*/
22 const esp_efuse_range_addr_t range_read_addr_blocks[] = {
23 {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
24 {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
25 {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
26 {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
27 {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
28 {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
29 {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
30 {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
31 {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
32 {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
33 {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
34 };
35
36 static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
37
38 /*Range addresses to write blocks (it is not real regs, it is buffer) */
39 const esp_efuse_range_addr_t range_write_addr_blocks[] = {
40 {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
41 {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
42 {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
43 {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
44 {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
45 {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
46 {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
47 {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
48 {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
49 {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
50 {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
51 };
52
53 #ifndef CONFIG_EFUSE_VIRTUAL
54 // Update Efuse timing configuration
esp_efuse_set_timing(void)55 static esp_err_t esp_efuse_set_timing(void)
56 {
57 // efuse clock is fixed.
58 // An argument (0) is for compatibility and will be ignored.
59 efuse_hal_set_timing(0);
60 return ESP_OK;
61 }
62 #endif // ifndef CONFIG_EFUSE_VIRTUAL
63
64 // Efuse read operation: copies data from physical efuses to efuse read registers.
esp_efuse_utility_clear_program_registers(void)65 void esp_efuse_utility_clear_program_registers(void)
66 {
67 efuse_hal_read();
68 efuse_hal_clear_program_registers();
69 }
70
esp_efuse_utility_check_errors(void)71 esp_err_t esp_efuse_utility_check_errors(void)
72 {
73 if (efuse_ll_get_err_rst_enable()) {
74 for (unsigned i = 0; i < 5; i++) {
75 uint32_t error_reg = REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4);
76 if (error_reg) {
77 uint32_t data_reg = REG_READ(EFUSE_RD_REPEAT_DATA0_REG + i * 4);
78 if (error_reg & data_reg) {
79 // For 0001 situation (4x coding scheme):
80 // an error bit points that data bit is wrong in case the data bit equals 1. (need to reboot in this case).
81 ESP_EARLY_LOGE(TAG, "Error in EFUSE_RD_REPEAT_DATA%d_REG of BLOCK0 (error_reg=0x%08x, data_reg=0x%08x). Need to reboot", i, error_reg, data_reg);
82 efuse_hal_read();
83 return ESP_FAIL;
84 }
85 }
86 }
87 }
88 return ESP_OK;
89 }
90
91 // Burn values written to the efuse write registers
esp_efuse_utility_burn_chip(void)92 esp_err_t esp_efuse_utility_burn_chip(void)
93 {
94 esp_err_t error = ESP_OK;
95 #ifdef CONFIG_EFUSE_VIRTUAL
96 ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
97 for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
98 int subblock = 0;
99 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
100 virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
101 }
102 }
103 #ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
104 esp_efuse_utility_write_efuses_to_flash();
105 #endif
106 #else // CONFIG_EFUSE_VIRTUAL
107 if (esp_efuse_set_timing() != ESP_OK) {
108 ESP_LOGE(TAG, "Efuse fields are not burnt");
109 } else {
110 // Permanently update values written to the efuse write registers
111 // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
112 for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
113 bool need_burn_block = false;
114 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
115 if (REG_READ(addr_wr_block) != 0) {
116 need_burn_block = true;
117 break;
118 }
119 }
120 if (!need_burn_block) {
121 continue;
122 }
123 if (error) {
124 // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
125 // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
126 ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
127 continue;
128 }
129 efuse_hal_clear_program_registers();
130 if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
131 uint8_t block_rs[12];
132 efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
133 hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
134 }
135 unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
136 unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
137 memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
138
139 uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
140 hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
141 int repeat_burn_op = 1;
142 bool correct_written_data;
143 bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block);
144 if (coding_error_before) {
145 ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
146 }
147 bool coding_error_occurred;
148
149 do {
150 ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
151 efuse_hal_program(num_block); // BURN a block
152
153 bool coding_error_after;
154 for (unsigned i = 0; i < 5; i++) {
155 efuse_hal_read();
156 coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
157 if (coding_error_after == true) {
158 break;
159 }
160 }
161 coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false;
162 if (coding_error_occurred) {
163 ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
164 }
165
166 correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len);
167 if (!correct_written_data || coding_error_occurred) {
168 ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
169 hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
170 }
171
172 } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
173
174 if (coding_error_occurred) {
175 ESP_LOGW(TAG, "Coding error was not fixed");
176 if (num_block == 0) {
177 ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
178 error = ESP_FAIL;
179 }
180 }
181 if (!correct_written_data) {
182 ESP_LOGE(TAG, "Written data are incorrect");
183 error = ESP_FAIL;
184 }
185 }
186 }
187 #endif // CONFIG_EFUSE_VIRTUAL
188 esp_efuse_utility_reset();
189 return error;
190 }
191
192 // After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
193 // This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
194 // The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
195 // They will be filled during the burn operation.
esp_efuse_utility_apply_new_coding_scheme()196 esp_err_t esp_efuse_utility_apply_new_coding_scheme()
197 {
198 // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
199 for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
200 if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
201 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
202 if (REG_READ(addr_wr_block)) {
203 int num_reg = 0;
204 for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
205 if (esp_efuse_utility_read_reg(num_block, num_reg)) {
206 ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
207 return ESP_ERR_CODING;
208 }
209 }
210 break;
211 }
212 }
213 }
214 }
215 return ESP_OK;
216 }
217
