1 /*
2 * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <stdint.h>
7 #include "sdkconfig.h"
8 #include "esp_attr.h"
9 #include "esp_log.h"
10 #include "esp_image_format.h"
11 #include "flash_qio_mode.h"
12 #include "soc/efuse_reg.h"
13 #include "soc/gpio_sig_map.h"
14 #include "soc/io_mux_reg.h"
15 #include "soc/assist_debug_reg.h"
16 #include "esp_cpu.h"
17 #include "soc/dport_reg.h"
18 #include "soc/rtc.h"
19 #include "soc/rtc_cntl_reg.h"
20 #include "soc/spi_periph.h"
21 #include "soc/extmem_reg.h"
22
23 #include "esp_rom_gpio.h"
24 #include "esp_rom_efuse.h"
25 #include "esp_rom_sys.h"
26 #include "esp_rom_spiflash.h"
27 #include "esp32s3/rom/rtc.h"
28
29 #include "bootloader_common.h"
30 #include "bootloader_init.h"
31 #include "bootloader_clock.h"
32 #include "bootloader_flash_config.h"
33 #include "bootloader_mem.h"
34 #include "bootloader_console.h"
35 #include "bootloader_flash_priv.h"
36 #include "bootloader_soc.h"
37 #include "esp_private/bootloader_flash_internal.h"
38 #include "esp_efuse.h"
39 #include "hal/mmu_hal.h"
40 #include "hal/cache_hal.h"
41 #include "xtensa/config/core.h"
42 #include "xt_instr_macros.h"
43 #ifdef CONFIG_ESP_SIMPLE_BOOT
44 #include "esp_flash_internal.h"
45 #endif
46
47 static const char *TAG = "boot.esp32s3";
48
wdt_reset_cpu0_info_enable(void)49 static void wdt_reset_cpu0_info_enable(void)
50 {
51 REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
52 REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
53 REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG, 1);
54 REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG, 1);
55 }
56
wdt_reset_info_dump(int cpu)57 static void wdt_reset_info_dump(int cpu)
58 {
59 uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
60 lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
61 const char *cpu_name = cpu ? "APP" : "PRO";
62
63 stat = 0xdeadbeef;
64 pid = 0;
65 if (cpu == 0) {
66 inst = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG);
67 dstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG);
68 data = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG);
69 pc = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG);
70 lsstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG);
71 lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG);
72 lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG);
73 } else {
74 #if !CONFIG_FREERTOS_UNICORE
75 inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG);
76 dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG);
77 data = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG);
78 pc = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG);
79 lsstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG);
80 lsaddr = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG);
81 lsdata = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG);
82 #else
83 ESP_EARLY_LOGE(TAG, "WDT reset info: %s CPU not support!\n", cpu_name);
84 return;
85 #endif
86 }
87
88 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
89 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
90 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
91 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
92 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
93 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
94 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
95 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
96 ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
97 }
98
bootloader_check_wdt_reset(void)99 static void bootloader_check_wdt_reset(void)
100 {
101 int wdt_rst = 0;
102 soc_reset_reason_t rst_reas[2];
103
104 rst_reas[0] = esp_rom_get_reset_reason(0);
105 rst_reas[1] = esp_rom_get_reset_reason(1);
106 if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
107 rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
108 ESP_EARLY_LOGW(TAG, "PRO CPU has been reset by WDT.");
109 wdt_rst = 1;
110 }
111 if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
112 rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
113 ESP_EARLY_LOGW(TAG, "APP CPU has been reset by WDT.");
114 wdt_rst = 1;
115 }
116 if (wdt_rst) {
117 // if reset by WDT dump info from trace port
118 wdt_reset_info_dump(0);
119 #if !CONFIG_FREERTOS_UNICORE
120 wdt_reset_info_dump(1);
121 #endif
122 }
123 wdt_reset_cpu0_info_enable();
124 }
125
bootloader_super_wdt_auto_feed(void)126 static void bootloader_super_wdt_auto_feed(void)
127 {
128 REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
129 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
130 REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
131 }
132
bootloader_ana_reset_config(void)133 static inline void bootloader_ana_reset_config(void)
134 {
135 //Enable WDT, BOD, and GLITCH reset
136 bootloader_ana_super_wdt_reset_config(true);
137 bootloader_ana_bod_reset_config(true);
138 bootloader_ana_clock_glitch_reset_config(true);
139 }
140
bootloader_init(void)141 esp_err_t bootloader_init(void)
142 {
143 esp_err_t ret = ESP_OK;
144
145 #if XCHAL_ERRATUM_572
146 uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
147 WSR(MEMCTL, memctl);
148 #endif // XCHAL_ERRATUM_572
149
150 bootloader_ana_reset_config();
151 bootloader_super_wdt_auto_feed();
152
153 // In RAM_APP, memory will be initialized in `call_start_cpu0`
154 #if !CONFIG_APP_BUILD_TYPE_RAM
155 // protect memory region
156 bootloader_init_mem();
157 /* check that static RAM is after the stack */
158 #ifndef NDEBUG
159 {
160 assert(&_bss_start <= &_bss_end);
161 assert(&_data_start <= &_data_end);
162 }
163 #endif
164 #ifndef __ZEPHYR__
165 // clear bss section
166 bootloader_clear_bss_section();
167 #endif
168 #endif // !CONFIG_APP_BUILD_TYPE_RAM
169
170 // init eFuse virtual mode (read eFuses to RAM)
171 #ifdef CONFIG_EFUSE_VIRTUAL
172 ESP_EARLY_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
173 #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
174 esp_efuse_init_virtual_mode_in_ram();
175 #endif
176 #endif
177 // config clock
178 bootloader_clock_configure();
179 // initialize console, from now on, we can use esp_log
180 bootloader_console_init();
181 /* print 2nd bootloader banner */
182 bootloader_print_banner();
183
184 #ifdef CONFIG_ESP_SIMPLE_BOOT
185 esp_flash_init_default_chip();
186 #endif
187
188 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
189 //init cache hal
190 cache_hal_init();
191 //init mmu
192 mmu_hal_init();
193 // update flash ID
194 /* disabled it to enable octal support */
195 // bootloader_flash_update_id();
196 // Check and run XMC startup flow
197 if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
198 ESP_EARLY_LOGE(TAG, "failed when running XMC startup flow, reboot!");
199 return ret;
200 }
201 #if !CONFIG_APP_BUILD_TYPE_RAM
202 // read bootloader header
203 if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
204 return ret;
205 }
206 // read chip revision and check if it's compatible to bootloader
207 if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
208 return ret;
209 }
210 #endif // !CONFIG_APP_BUILD_TYPE_RAM
211 // initialize spi flash
212 if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
213 return ret;
214 }
215 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
216
217 // check whether a WDT reset happend
218 bootloader_check_wdt_reset();
219 // config WDT
220 bootloader_config_wdt();
221 // enable RNG early entropy source
222 bootloader_enable_random();
223 return ret;
224 }
225
