1 /*
2  * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include "app_cpu_start.h"
8 
9 #include "esp_rom_sys.h"
10 #include "soc/dport_reg.h"
11 #include "soc/gpio_periph.h"
12 #include "soc/rtc_periph.h"
13 #include "soc/rtc_cntl_reg.h"
14 #include "esp32s3/rom/cache.h"
15 #include "esp32s3/rom/uart.h"
16 #include "esp_cpu.h"
17 #include "esp_log.h"
18 
19 static const char *TAG = "app_cpu_start";
20 
appcpu_start(uint32_t entry_addr)21 void appcpu_start(uint32_t entry_addr)
22 {
23     ESP_LOGI(TAG, "Starting APPCPU");
24 
25     esp_cpu_unstall(1);
26 
27     // Enable clock and reset APP CPU. Note that OpenOCD may have already
28     // enabled clock and taken APP CPU out of reset. In this case don't reset
29     // APP CPU again, as that will clear the breakpoints which may have already
30     // been set.
31     if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
32         REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
33         REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
34         REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
35         REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
36     }
37 
38     ets_set_appcpu_boot_addr(entry_addr);
39     esp_rom_delay_us(10000);
40     uart_tx_wait_idle(0);
41     ESP_LOGI(TAG, "APPCPU start sequence complete");
42 }
43