1ESP32-Ethernet-Kit V1.2 Getting Started Guide
2=============================================
3
4:link_to_translation:`zh_CN:[中文]`
5
6This guide shows how to get started with the ESP32-Ethernet-Kit development board and also provides information about its functionality and configuration options.
7
8The :ref:`ESP32-Ethernet-Kit <get-started-esp32-ethernet-kit-v1.2>` is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide more flexible power supply options, the ESP32-Ethernet-Kit also supports power over Ethernet (PoE).
9
10.. _get-started-esp32-ethernet-kit-v1.2-overview:
11
12.. figure:: ../../../_static/esp32-ethernet-kit-v1.2-overview.png
13    :align: center
14    :scale: 80%
15    :alt: ESP32-Ethernet-Kit V1.2
16    :figclass: align-center
17
18    ESP32-Ethernet-Kit V1.2 Overview (click to enlarge)
19
20What You Need
21-------------
22
23* :ref:`ESP32-Ethernet-Kit V1.2 board <get-started-esp32-ethernet-kit-v1.2>`
24* USB 2.0 A to Micro B Cable
25* Computer running Windows, Linux, or macOS
26
27You can skip the introduction sections and go directly to Section `Start Application Development`_.
28
29Overview
30--------
31
32ESP32-Ethernet-Kit is an ESP32-based development board produced by `Espressif <https://espressif.com>`_.
33
34It consists of two development boards, the Ethernet board A and the PoE board B. The :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>` contains Bluetooth/Wi-Fi dual-mode ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet functionality. The A board can work independently, without the board B installed.
35
36.. _get-started-esp32-ethernet-kit-v1.2:
37
38.. figure:: ../../../_static/esp32-ethernet-kit-v1.2.jpg
39    :align: center
40    :scale: 80%
41    :alt: ESP32-Ethernet-Kit V1.2
42    :figclass: align-center
43
44    ESP32-Ethernet-Kit V1.2 (click to enlarge)
45
46For the application loading and monitoring, the Ethernet board (A) also features FTDI FT2232H chip - an advanced multi-interface USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface without a separate JTAG debugger.
47
48
49Functionality Overview
50----------------------
51
52The block diagram below shows the main components of ESP32-Ethernet-Kit and their interconnections.
53
54.. figure:: ../../../_static/esp32-ethernet-kit-v1.1-block-diagram.png
55    :align: center
56    :scale: 60%
57    :alt: ESP32-Ethernet-Kit block diagram (click to enlarge)
58    :figclass: align-center
59
60    ESP32-Ethernet-Kit block diagram (click to enlarge)
61
62
63Functional Description
64----------------------
65
66The following figures and tables describe the key components, interfaces, and controls of the ESP32-Ethernet-Kit.
67
68
69.. _get-started-esp32-ethernet-kit-a-v1.2-layout:
70
71Ethernet Board (A)
72^^^^^^^^^^^^^^^^^^
73
74.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.2-layout.jpg
75    :align: center
76    :scale: 80%
77    :alt: ESP32-Ethernet-Kit V1.2 (click to enlarge)
78    :figclass: align-center
79
80    ESP32-Ethernet-Kit - Ethernet board (A) layout (click to enlarge)
81
82The table below provides description starting from the picture's top right corner and going clockwise.
83
84==================  ===========================================================================
85Key Component       Description
86==================  ===========================================================================
87ESP32-WROVER-E      This ESP32 module features 64-Mbit PSRAM for flexible extended storage and data processing capabilities.
88
89GPIO Header 2       Five unpopulated through-hole solder pads to provide access to selected GPIOs of ESP32. For details, see `GPIO Header 2`_.
90
91Function Switch     A 4-bit DIP switch used to configure the functionality of selected GPIOs of ESP32. For details see `Function Switch`_.
92
93
94Tx/Rx LEDs          Two LEDs to show the status of UART transmission.
95
96FT2232H             The FT2232H chip serves as a multi-protocol USB-to-serial bridge which can be programmed and controlled via USB to provide communication with ESP32. FT2232H also features USB-to-JTAG interface which is available on channel A of the chip, while USB-to-serial is on channel B. The FT2232H chip enhances user-friendliness in terms of application development and debugging. See `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_.
97
98USB Port            USB interface. Power supply for the board as well as the communication interface between a computer and the board.
99
100Power Switch        Power On/Off Switch. Toggling the switch to **5V0** position powers the board on, toggling to **GND** position powers the board off.
101
1025V Input            The 5V power supply interface can be more convenient when the board is operating autonomously (not connected to a computer).
103
1045V Power On LED     This red LED turns on when power is supplied to the board, either from USB or 5V Input.
105
106DC/DC Converter     Provided DC 5 V to 3.3 V conversion, output current up to 2 A.
107
108Board B Connectors  A pair male and female header pins for mounting the `PoE board (B)`_.
109
110IP101GRI (PHY)      The physical layer (PHY) connection to the Ethernet cable is implemented using the `IP101GRI <http://www.bdtic.com/DataSheet/ICplus/IP101G_DS_R01_20121224.pdf>`_ chip. The connection between PHY and ESP32 is done through the reduced media-independent interface (RMII), a variant of the media-independent interface `(MII) <https://en.wikipedia.org/wiki/Media-independent_interface>`_ standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100 Mbps.
111
112RJ45 Port           Ethernet network data transmission port.
113
114Magnetics Module    The Magnetics are part of the Ethernet specification to protect against faults and transients, including rejection of common mode signals between the transceiver IC and the cable. The magnetics also provide galvanic isolation between the transceiver and the Ethernet device.
115
116Link/Activity LEDs  Two LEDs (green and red) that respectively indicate the "Link" and "Activity" statuses of the PHY.
117
118BOOT Button         Download button. Holding down **BOOT** and then pressing **EN** initiates Firmware Download mode for downloading firmware through the serial port.
119
120EN Button           Reset button.
121
122GPIO Header 1       This header provides six unpopulated through-hole solder pads connected to spare GPIOs of ESP32. For details, see `GPIO Header 1`_.
123
124==================  ===========================================================================
125
126.. note::
127
128    Automatic firmware download is supported. If following steps and using software described in Section `Start Application Development`_, users don't need to do any operation with BOOT button or EN button.
129
130PoE Board (B)
131^^^^^^^^^^^^^
132
133This board coverts power delivered over the Ethernet cable (PoE) to provide a power supply for the Ethernet board (A). The main components of the PoE board (B) are shown on the block diagram under `Functionality Overview`_.
134
135The PoE board (B) has the following features:
136
137* Support for IEEE 802.3at
138* Power output: 5 V, 1.4 A
139
140To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet board (A) should be connected with an Ethernet cable to a switch that supports PoE. When the Ethernet board (A) detects 5 V power output from the PoE board (B), the USB power will be automatically cut off.
141
142.. figure:: ../../../_static/esp32-ethernet-kit-b-v1.0-layout.png
143    :align: center
144    :scale: 80%
145    :alt: ESP32-Ethernet-Kit - PoE board (B)
146    :figclass: align-center
147
148    ESP32-Ethernet-Kit - PoE board (B) layout (click to enlarge)
149
150.. list-table:: Table  PoE board (B)
151  :widths: 40 150
152  :header-rows: 1
153
154  * - Key Component
155    - Description
156  * - Board A Connector
157    - Four female (left) and four male (right) header pins for connecting the PoE board (B) to :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>`. The pins on the left accept power coming from a PoE switch. The pins on the right deliver 5 V power supply to the  Ethernet board (A).
158  * - External Power Terminals
159    - Optional power supply (26.6 ~ 54 V) to the PoE board (B).
160
161.. _get-started-esp32-ethernet-kit-v1.2-setup-options:
162
163Setup Options
164-------------
165
166This section describes options to configure the ESP32-Ethernet-Kit hardware.
167
168
169Function Switch
170^^^^^^^^^^^^^^^
171
172When in On position, this DIP switch is routing listed GPIOs to FT2232H to provide JTAG functionality. When in Off position, the GPIOs may be used for other purposes.
173
174=======  ================
175DIP SW   GPIO Pin
176=======  ================
177 1       GPIO13
178 2       GPIO12
179 3       GPIO15
180 4       GPIO14
181=======  ================
182
183
184RMII Clock Selection
185^^^^^^^^^^^^^^^^^^^^
186
187The ethernet MAC and PHY under RMII working mode need a common 50 MHz reference clock (i.e. RMII clock) that can be provided either externally, or generated from internal ESP32 APLL (not recommended).
188
189.. note::
190
191    For additional information on the RMII clock selection, please refer to `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_, sheet 2, location D2.
192
193RMII Clock Sourced Externally by PHY
194""""""""""""""""""""""""""""""""""""
195
196By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency multiplication of 25 MHz crystal connected to the PHY. For details, please see the figure below.
197
198.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-from-phy.png
199    :align: center
200    :scale: 80%
201    :alt: RMII Clock from IP101GRI PHY
202    :figclass: align-center
203
204    RMII Clock from IP101GRI PHY
205
206Please note that the PHY is reset on power up by pulling the RESET_N signal down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter download mode (when the clock signal of REF_CLK_50M is at a high logic level during the GPIO0 power-up sampling phase).
207
208RMII Clock Sourced Internally from ESP32's APLL
209"""""""""""""""""""""""""""""""""""""""""""""""
210
211Another option is to source the RMII Clock from internal ESP32 APLL, see figure below. The clock signal coming from GPIO0 is first inverted, to account for transmission line delay, and then supplied to the PHY.
212
213
214.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-to-phy.png
215    :align: center
216    :scale: 80%
217    :alt: RMII Clock from ESP Internal APLL
218    :figclass: align-center
219
220    RMII Clock from ESP Internal APLL
221
222To implement this option, users need to remove or add some RC components on the board. For details please refer to `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_, sheet 2, location D2. Please note that if the APLL is already used for other purposes (e.g. I2S peripheral), then you have no choice but use an external RMII clock.
223
224GPIO Allocation
225---------------
226
227This section describes allocation of ESP32 GPIOs to specific interfaces or functions of the ESP32-Ethernet-Kit.
228
229
230IP101GRI (PHY) Interface
231^^^^^^^^^^^^^^^^^^^^^^^^
232
233The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table below. Implementation of ESP32-Ethernet-Kit defaults to Reduced Media-Independent Interface (RMII).
234
235====  ================  ===============
236No.   ESP32 Pin (MAC)   IP101GRI (PHY)
237====  ================  ===============
238*RMII Interface*
239---------------------------------------
240 1    GPIO21            TX_EN
241 2    GPIO19            TXD[0]
242 3    GPIO22            TXD[1]
243 4    GPIO25            RXD[0]
244 5    GPIO26            RXD[1]
245 6    GPIO27            CRS_DV
246 7    GPIO0             REF_CLK
247----  ----------------  ---------------
248*Serial Management Interface*
249---------------------------------------
250 8    GPIO23            MDC
251 9    GPIO18            MDIO
252----  ----------------  ---------------
253*PHY Reset*
254---------------------------------------
25510    GPIO5             Reset_N
256====  ================  ===============
257
258.. note::
259
260    The allocation of all pins under the ESP32's *RMII Interface* is fixed and cannot be changed either through IO MUX or GPIO Matrix. REF_CLK can only be selected from GPIO0, GPIO16 or GPIO17 and it can not be changed through GPIO Matrix.
261
262
263GPIO Header 1
264^^^^^^^^^^^^^
265
266This header exposes some GPIOs that are not used elsewhere on the ESP32-Ethernet-Kit.
267
268====  ================
269No.   ESP32 Pin
270====  ================
271 1    GPIO32
272 2    GPIO33
273 3    GPIO34
274 4    GPIO35
275 5    GPIO36
276 6    GPIO39
277====  ================
278
279
280GPIO Header 2
281^^^^^^^^^^^^^
282
283This header contains GPIOs that may be used for other purposes depending on scenarios described in column "Comments".
284
285====  ==========  ====================
286No.   ESP32 Pin   Comments
287====  ==========  ====================
288 1    GPIO17      See note 1
289 2    GPIO16      See note 1
290 3    GPIO4
291 4    GPIO2
292 5    GPIO13      See note 2
293 6    GPIO12      See note 2
294 7    GPIO15      See note 2
295 8    GPIO14      See note 2
296 9    GND         Ground
29710    3V3         3.3 V power supply
298====  ==========  ====================
299
300.. note::
301
302    1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-E module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
303
304    2. Functionality depends on the settings of the `Function Switch`_.
305
306
307GPIO Allocation Summary
308^^^^^^^^^^^^^^^^^^^^^^^
309
310.. csv-table::
311    :header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments
312
313    S_VP,,,,IO36,
314    S_VN,,,,IO39,
315    IO34,,,,IO34,
316    IO35,,,,IO35,
317    IO32,,,,IO32,
318    IO33,,,,IO33,
319    IO25,RXD[0],,,,
320    IO26,RXD[1],,,,
321    IO27,CRS_DV,,,,
322    IO14,,,TMS,IO14,
323    IO12,,,TDI,IO12,
324    IO13,,,TCK,IO13,
325    IO15,,,TDO,IO15,
326    IO2,,,,IO2,
327    IO0,REF_CLK,,,,See note 1
328    IO4,,,,IO4,
329    IO16,,,,IO16 (NC),See note 2
330    IO17,,,,IO17 (NC),See note 2
331    IO5,Reset_N,,,,See note 1
332    IO18,MDIO,,,,
333    IO19,TXD[0],,,,
334    IO21,TX_EN,,,,
335    RXD0,,RXD,,,
336    TXD0,,TXD,,,
337    IO22,TXD[1],,,,
338    IO23,MDC,,,,
339
340.. note::
341
342    1. To prevent the power-on state of the GPIO0 from being affected by the clock output on the PHY side, the RESET_N signal to PHY defaults to low, turning the clock output off. After power-on you can control RESET_N with GPIO5 to turn the clock output on. See also `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off the clock output through RESET_N, it is recommended to use a crystal module that can be disabled/enabled externally. Similarly like when using RESET_N, the oscillator module should be disabled by default and turned on by ESP32 after power-up. For a reference design please see `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_.
343
344    2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-E module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
345
346
347Start Application Development
348-----------------------------
349
350Before powering up your ESP32-Ethernet-Kit, please make sure that the board is in good condition with no obvious signs of damage.
351
352Initial Setup
353^^^^^^^^^^^^^
354
3551. Set the **Function Switch** on the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>` to its default position by turning all the switches to **ON**.
3562. To simplify flashing and testing of the application, do not input extra signals to the board headers.
3573. The `PoE board (B)`_ can now be plugged in, but do not connect external power to it.
3584. Connect the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>` to the PC with a USB cable.
3595. Turn the **Power Switch** from GND to 5V0 position, the **5V Power On LED** should light up.
360
361
362Now to Development
363^^^^^^^^^^^^^^^^^^
364
365Proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an example project onto your board.
366
367Move on to the next section only if you have successfully completed all the above steps.
368
369
370Configure and Load the Ethernet Example
371^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
372
373After setting up the development environment and testing the board, you can configure and flash the :example:`ethernet/basic` example. This example has been created for testing Ethernet functionality. It supports different PHY, including **IP101GRI** installed on :ref:`get-started-esp32-ethernet-kit-v1.2`.
374
375
376Summary of Changes from ESP32-Ethernet-Kit V1.1
377-----------------------------------------------
378
379* Correct the placement of GPIO pin number marking on the board’s silkscreen besides the DIP switch.
380* Values of C1, C2, C42, and C43 are updated to 20 pF. For more information, please check `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_.
381* Replace ESP32-WROVER-B with ESP32-WROVER-E.
382
383
384Other Versions of ESP32-Ethernet-Kit
385------------------------------------
386
387* :doc:`get-started-ethernet-kit-v1.0`
388* :doc:`get-started-ethernet-kit-v1.1`
389
390
391Related Documents
392-----------------
393
394* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_ (PDF)
395* `ESP32-Ethernet-Kit PoE Board (B) Schematic`_ (PDF)
396* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) PCB Layout <https://dl.espressif.com/dl/schematics/PCB_ESP32-Ethernet-Kit_A_V1_2_20190829.pdf>`_ (PDF)
397* `ESP32-Ethernet-Kit PoE Board (B) PCB Layout <https://dl.espressif.com/dl/schematics/PCB_ESP32-Ethernet-Kit_B_V1_0_20190306.pdf>`_ (PDF)
398* `ESP32 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ (PDF)
399* `ESP32-WROVER-E Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf>`_ (PDF)
400* :doc:`../../api-guides/jtag-debugging/index`
401* :doc:`../../hw-reference/index`
402
403For other design documentation for the board, please contact us at sales@espressif.com.
404
405.. _ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.1_20190711.pdf
406.. _ESP32-Ethernet-Kit PoE board (B) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
407.. _ESP32-Ethernet-Kit V1.0 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
408.. _ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf
409
410.. toctree::
411    :hidden:
412
413    get-started-ethernet-kit-v1.0.rst
414    get-started-ethernet-kit-v1.1.rst
415
416