1ESP32-Ethernet-Kit V1.1 Getting Started Guide
2=============================================
3
4:link_to_translation:`zh_CN:[中文]`
5
6This guide shows how to get started with the ESP32-Ethernet-Kit development board and also provides information about its functionality and configuration options.
7
8The :ref:`ESP32-Ethernet-Kit <get-started-esp32-ethernet-kit-v1.1>` is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide more flexible power supply options, the ESP32-Ethernet-Kit also supports power over Ethernet (PoE).
9
10What You Need
11-------------
12
13* :ref:`ESP32-Ethernet-Kit V1.1 board <get-started-esp32-ethernet-kit-v1.1>`
14* USB 2.0 A to Micro B Cable
15* Computer running Windows, Linux, or macOS
16
17You can skip the introduction sections and go directly to Section `Start Application Development`_.
18
19Overview
20--------
21
22ESP32-Ethernet-Kit is an ESP32-based development board produced by `Espressif <https://espressif.com>`_.
23
24It consists of two development boards, the Ethernet board A and the PoE board B. The :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` contains Bluetooth / Wi-Fi dual-mode ESP32-WROVER-B module and IP101GRI, a Single Port 10/100 Fast Ethernet Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet functionality. The A board can work independently, without the board B installed.
25
26.. _get-started-esp32-ethernet-kit-v1.1:
27
28.. figure:: ../../../_static/esp32-ethernet-kit-v1.1.png
29    :align: center
30    :alt: ESP32-Ethernet-Kit V1.1
31    :figclass: align-center
32
33    ESP32-Ethernet-Kit V1.1
34
35For the application loading and monitoring, the Ethernet board (A) also features FTDI FT2232H chip - an advanced multi-interface USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface without a separate JTAG debugger.
36
37
38Functionality Overview
39----------------------
40
41The block diagram below shows the main components of ESP32-Ethernet-Kit and their interconnections.
42
43.. figure:: ../../../_static/esp32-ethernet-kit-v1.1-block-diagram.png
44    :align: center
45    :scale: 60%
46    :alt: ESP32-Ethernet-Kit block diagram (click to enlarge)
47    :figclass: align-center
48
49    ESP32-Ethernet-Kit block diagram (click to enlarge)
50
51
52Functional Description
53----------------------
54
55The following figures and tables describe the key components, interfaces, and controls of the ESP32-Ethernet-Kit.
56
57
58.. _get-started-esp32-ethernet-kit-a-v1.1-layout:
59
60Ethernet Board (A)
61^^^^^^^^^^^^^^^^^^
62
63.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.1-layout.png
64    :align: center
65    :scale: 80%
66    :alt: ESP32-Ethernet-Kit - Ethernet board (A) layout
67    :figclass: align-center
68
69    ESP32-Ethernet-Kit - Ethernet board (A) layout (click to enlarge)
70
71The table below provides description starting from the picture's top right corner and going clockwise.
72
73==================  ===========================================================================
74Key Component       Description
75==================  ===========================================================================
76ESP32-WROVER-B      This ESP32 module features 64-Mbit PSRAM for flexible extended storage and data processing capabilities.
77
78GPIO Header 2       Five unpopulated through-hole solder pads to provide access to selected GPIOs of ESP32. For details, see `GPIO Header 2`_.
79
80Function Switch     A 4-bit DIP switch used to configure the functionality of selected GPIOs of ESP32. Please note that placement of GPIO pin number marking on the board's silkscreen besides the DIP switch is incorrect. For details and correct pin allocation see `Function Switch`_.
81
82Tx/Rx LEDs          Two LEDs to show the status of UART transmission.
83
84FT2232H             The FT2232H chip serves as a multi-protocol USB-to-serial bridge which can be programmed and controlled via USB to provide communication with ESP32. FT2232H also features USB-to-JTAG interface which is available on channel A of the chip, while USB-to-serial is on channel B. The FT2232H chip enhances user-friendliness in terms of application development and debugging. See `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_.
85
86USB Port            USB interface. Power supply for the board as well as the communication interface between a computer and the board.
87
88Power Switch        Power On/Off Switch. Toggling the switch to **5V0** position powers the board on, toggling to **GND** position powers the board off.
89
905V Input            The 5V power supply interface can be more convenient when the board is operating autonomously (not connected to a computer).
91
925V Power On LED     This red LED turns on when power is supplied to the board, either from USB or 5V Input.
93
94DC/DC Converter     Provided DC 5 V to 3.3 V conversion, output current up to 2A.
95
96Board B Connectors  A pair male and female header pins for mounting the `PoE board (B)`_.
97
98IP101GRI (PHY)      The physical layer (PHY) connection to the Ethernet cable is implemented using the `IP101GRI <http://www.bdtic.com/DataSheet/ICplus/IP101G_DS_R01_20121224.pdf>`_ chip. The connection between PHY and ESP32 is done through the reduced media-independent interface (RMII), a variant of the media-independent interface `(MII) <https://en.wikipedia.org/wiki/Media-independent_interface>`_ standard. The PHY supports the IEEE 802.3 / 802.3u standard of 10/100Mbps.
99
100RJ45 Port           Ethernet network data transmission port.
101
102Magnetics Module    The Magnetics are part of the Ethernet specification to protect against faults and transients, including rejection of common mode signals between the transceiver IC and the cable. The magnetics also provide galvanic isolation between the transceiver and the Ethernet device.
103
104Link/Activity LEDs  Two LEDs (green and red) that respectively indicate the "Link" and "Activity" statuses of the PHY.
105
106BOOT Button         Download button. Holding down **BOOT** and then pressing **EN** initiates Firmware Download mode for downloading firmware through the serial port.
107
108EN Button           Reset button.
109
110GPIO Header 1       This header provides six unpopulated through-hole solder pads connected to spare GPIOs of ESP32. For details, see `GPIO Header 1`_.
111
112==================  ===========================================================================
113
114PoE Board (B)
115^^^^^^^^^^^^^
116
117This board coverts power delivered over the Ethernet cable (PoE) to provide a power supply for the Ethernet board (A). The main components of the PoE board (B) are shown on the block diagram under `Functionality Overview`_.
118
119The PoE board (B) has the following features:
120
121* Support for IEEE 802.3at
122* Power output: 5 V, 1.4 A
123
124To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet board (A) should be connected with an Ethernet cable to a switch that supports PoE. When the Ethernet board (A) detects 5 V power output from the PoE board (B), the USB power will be automatically cut off.
125
126.. figure:: ../../../_static/esp32-ethernet-kit-b-v1.0-layout.png
127    :align: center
128    :scale: 80%
129    :alt: ESP32-Ethernet-Kit - PoE board (B)
130    :figclass: align-center
131
132    ESP32-Ethernet-Kit - PoE board (B) layout (click to enlarge)
133
134.. list-table:: Table  PoE board (B)
135  :widths: 40 150
136  :header-rows: 1
137
138  * - Key Component
139    - Description
140  * - Board A Connector
141    - Four female (left) and four male (right) header pins for connecting the PoE board (B) to :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>`. The pins on the left accept power coming from a PoE switch. The pins on the right deliver 5 V power supply to the  Ethernet board (A).
142  * - External Power Terminals
143    - Optional power supply (26.6 ~ 54 V) to the PoE board (B).
144
145.. _get-started-esp32-ethernet-kit-v1.1-setup-options:
146
147Setup Options
148-------------
149
150This section describes options to configure the ESP32-Ethernet-Kit hardware.
151
152
153Function Switch
154^^^^^^^^^^^^^^^
155
156When in On position, this DIP switch is routing listed GPIOs to FT2232H to provide JTAG functionality. When in Off position, the GPIOs may be used for other purposes.
157
158=======  ================
159DIP SW   GPIO Pin
160=======  ================
161 1       GPIO13
162 2       GPIO12
163 3       GPIO15
164 4       GPIO14
165=======  ================
166
167.. note::
168
169    Placement of GPIO pin number marking on the board's silkscreen besides the DIP switch is incorrect. Please use instead the pin order as in the table above.
170
171
172RMII Clock Selection
173^^^^^^^^^^^^^^^^^^^^
174
175The ethernet MAC and PHY under RMII working mode need a common 50 MHz reference clock (i.e. RMII clock) that can be provided either externally, or generated from internal ESP32 APLL.
176
177.. note::
178
179    For additional information on the RMII clock selection, please refer to `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_, sheet 2, location D2.
180
181RMII Clock Sourced Externally by PHY
182""""""""""""""""""""""""""""""""""""
183
184By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency multiplication of 25 MHz crystal connected to the PHY. For details, please see the figure below.
185
186.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-from-phy.png
187    :align: center
188    :scale: 80%
189    :alt: RMII Clock from IP101GRI PHY
190    :figclass: align-center
191
192    RMII Clock from IP101GRI PHY
193
194Please note that the PHY is reset on power up by pulling the RESET_N signal down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter download mode (when the clock signal of REF_CLK_50M is at a high logic level during the GPIO0 power-up sampling phase).
195
196RMII Clock Sourced Internally from ESP32's APLL
197"""""""""""""""""""""""""""""""""""""""""""""""
198
199Another option is to source the RMII Clock from internal ESP32 APLL, see figure below. The clock signal coming from GPIO0 is first inverted, to account for transmission line delay, and then supplied to the PHY.
200
201
202.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-to-phy.png
203    :align: center
204    :scale: 80%
205    :alt: RMII Clock from ESP Internal APLL
206    :figclass: align-center
207
208    RMII Clock from ESP Internal APLL
209
210To implement this option, users need to remove or add some RC components on the board. For details please refer to `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_, sheet 2, location D2. Please note that if the APLL is already used for other purposes (e.g. I2S peripheral), then you have no choice but use an external RMII clock.
211
212
213GPIO Allocation
214---------------
215
216This section describes allocation of ESP32 GPIOs to specific interfaces or functions of the ESP32-Ethernet-Kit.
217
218
219IP101GRI (PHY) Interface
220^^^^^^^^^^^^^^^^^^^^^^^^
221
222The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table below. Implementation of ESP32-Ethernet-Kit defaults to Reduced Media-Independent Interface (RMII).
223
224====  ================  ===============
225.     ESP32 Pin (MAC)   IP101GRI (PHY)
226====  ================  ===============
227*RMII Interface*
228---------------------------------------
229 1    GPIO21            TX_EN
230 2    GPIO19            TXD[0]
231 3    GPIO22            TXD[1]
232 4    GPIO25            RXD[0]
233 5    GPIO26            RXD[1]
234 6    GPIO27            CRS_DV
235 7    GPIO0             REF_CLK
236----  ----------------  ---------------
237*Serial Management Interface*
238---------------------------------------
239 8    GPIO23            MDC
240 9    GPIO18            MDIO
241----  ----------------  ---------------
242*PHY Reset*
243---------------------------------------
24410    GPIO5             Reset_N
245====  ================  ===============
246
247.. note::
248
249    Except for REF_CLK, the allocation of all pins under the ESP32's *RMII Interface* is fixed and cannot be changed either through IOMUX or GPIO Matrix.
250
251
252GPIO Header 1
253^^^^^^^^^^^^^
254
255This header exposes some GPIOs that are not used elsewhere on the ESP32-Ethernet-Kit.
256
257====  ================
258.     ESP32 Pin
259====  ================
260 1    GPIO32
261 2    GPIO33
262 3    GPIO34
263 4    GPIO35
264 5    GPIO36
265 6    GPIO39
266====  ================
267
268
269GPIO Header 2
270^^^^^^^^^^^^^
271
272This header contains GPIOs that may be used for other purposes depending on scenarios described in column "Comments".
273
274====  ==========  ====================
275.     ESP32 Pin   Comments
276====  ==========  ====================
277 1    GPIO17      See note 1
278 2    GPIO16      See note 1
279 3    GPIO4
280 4    GPIO2
281 5    GPIO13      See note 2
282 6    GPIO12      See note 2
283 7    GPIO15      See note 2
284 8    GPIO14      See note 2
285 9    GND         Ground
28610    3V3         3.3 V power supply
287====  ==========  ====================
288
289.. note::
290
291    1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-B module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
292
293    2. Functionality depends on the settings of the `Function Switch`_.
294
295
296GPIO Allocation Summary
297^^^^^^^^^^^^^^^^^^^^^^^
298
299.. csv-table::
300    :header: ESP32-WROVER-B,IP101GRI,UART,JTAG,GPIO,Comments
301
302    S_VP,,,,IO36,
303    S_VN,,,,IO39,
304    IO34,,,,IO34,
305    IO35,,,,IO35,
306    IO32,,,,IO32,
307    IO33,,,,IO33,
308    IO25,RXD[0],,,,
309    IO26,RXD[1],,,,
310    IO27,CRS_DV,,,,
311    IO14,,,TMS,IO14,
312    IO12,,,TDI,IO12,
313    IO13,,RTS,TCK,IO13,
314    IO15,,CTS,TDO,IO15,
315    IO2,,,,IO2,
316    IO0,REF_CLK,,,,See note 1
317    IO4,,,,IO4,
318    IO16,,,,IO16 (NC),See note 2
319    IO17,,,,IO17 (NC),See note 2
320    IO5,Reset_N,,,,See note 1
321    IO18,MDIO,,,,
322    IO19,TXD[0],,,,
323    IO21,TX_EN,,,,
324    RXD0,,RXD,,,
325    TXD0,,TXD,,,
326    IO22,TXD[1],,,,
327    IO23,MDC,,,,
328
329.. note::
330
331    1. To prevent the power-on state of the GPIO0 from being affected by the clock output on the PHY side, the RESET_N signal to PHY defaults to low, turning the clock output off. After power-on you can control RESET_N with GPIO5 to turn the clock output on. See also `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off the clock output through RESET_N, it is recommended to use a crystal module that can be disabled / enabled externally. Similarly like when using RESET_N, the oscillator module should be disabled by default and turned on by ESP32 after power-up. For a reference design please see `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_.
332
333    2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-B module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
334
335
336Start Application Development
337-----------------------------
338
339Before powering up your ESP32-Ethernet-Kit, please make sure that the board is in good condition with no obvious signs of damage.
340
341Initial Setup
342^^^^^^^^^^^^^
343
3441. Set the **Function Switch** on the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` to its default position by turning all the switches to **ON**.
3452. To simplify flashing and testing of the application, do not input extra signals to the board headers.
3463. The `PoE board (B)`_ can now be plugged in, but do not connect external power to it.
3474. Connect the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` to the PC with a USB cable.
3485. Turn the **Power Switch** from GND to 5V0 position, the **5V Power On LED** should light up.
349
350
351Now to Development
352^^^^^^^^^^^^^^^^^^
353
354Proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an example project onto your board.
355
356Move on to the next section only if you have successfully completed all the above steps.
357
358
359Configure and Load the Ethernet Example
360^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
361
362After setting up the development environment and testing the board, you can configure and flash the :example:`ethernet/basic` example. This example has been created for testing Ethernet functionality. It supports different PHY, including **IP101GRI** installed on :ref:`get-started-esp32-ethernet-kit-v1.1`.
363
364
365Summary of Changes from ESP32-Ethernet-Kit V1.0
366-----------------------------------------------
367
368* The original inverted clock provided to the PHY by ESP32 using GPIO0 has been replaced by a clock generated on PHY side. The PHY's clock is connected to the ESP32 with same GPIO0. The GPIO2 which was originally used to control the active crystal oscillator on the PHY side, can now be used for other purposes.
369* On power up, the ESP32 boot strapping pin GPIO0 may be affected by clock generated on the PHY side. To resolve this issue the PHY's Reset-N signal is pulled low using resistor R17 and effectively turning off the PHY's clock output. The Reset-N signal can be then pulled high by ESP32 using GPIO5.
370* Removed FT2232H chip's external SPI Flash U6.
371* Removed flow control jumper header J4.
372* Removed nTRST JTAG signal. The corresponding GPIO4 can now be used for other purposes.
373* Pull-up resistor R68 on the GPIO15 line is moved to the MTDO side of JTAG.
374* To make the A and B board connections more foolproof (reduce chances of plugging in the B board in reverse orientation), the original two 4-pin male rows on board A were changed to one 4-pin female row and one 4-pin male row. Corresponding male and female 4-pins rows were installed on board B.
375
376
377Other Versions of ESP32-Ethernet-Kit
378------------------------------------
379
380* :doc:`get-started-ethernet-kit-v1.0`
381
382
383Related Documents
384-----------------
385
386* `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_ (PDF)
387* `ESP32-Ethernet-Kit V1.0 PoE board (B) schematic`_ (PDF)
388* `ESP32 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ (PDF)
389* `ESP32-WROVER-B Datasheet <https://espressif.com/sites/default/files/documentation/esp32-wrover-b_datasheet_en.pdf>`_ (PDF)
390* :doc:`../../api-guides/jtag-debugging/index`
391* :doc:`../../hw-reference/index`
392
393For other design documentation for the board, please contact us at sales@espressif.com.
394
395.. _ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.1_20190711.pdf
396.. _ESP32-Ethernet-Kit V1.0 PoE board (B) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
397.. _ESP32-Ethernet-Kit V1.0 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
398
399.. toctree::
400    :hidden:
401
402    get-started-ethernet-kit-v1.0.rst
403