1 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "ulp_riscv/ulp_riscv.h"
16 #include "ulp_riscv/ulp_riscv_utils.h"
17
ulp_riscv_rescue_from_monitor(void)18 void ulp_riscv_rescue_from_monitor(void)
19 {
20 /* Rescue RISCV from monitor state. */
21 CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
22 }
23
ulp_riscv_wakeup_main_processor(void)24 void ulp_riscv_wakeup_main_processor(void)
25 {
26 SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SW_CPU_INT);
27 }
28
ulp_riscv_shutdown(void)29 void ulp_riscv_shutdown(void)
30 {
31 /* Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time. */
32 REG_SET_FIELD(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_2_CLK_DIS, 0x3F);
33
34 /* suspends the ulp operation*/
35 SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
36
37 /* Resets the processor */
38 SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
39
40 while(1);
41 }
42
ulp_riscv_delay_cycles(uint32_t cycles)43 void ulp_riscv_delay_cycles(uint32_t cycles)
44 {
45 uint32_t start = ULP_RISCV_GET_CCOUNT();
46
47 while ((ULP_RISCV_GET_CCOUNT() - start) < cycles) {
48 /* Wait */
49 }
50 }
51
