1 // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdarg.h>
16 #include "sdkconfig.h"
17 #include "esp_flash.h"
18 #include "esp_attr.h"
19
20 #include "esp_rom_sys.h"
21 #if CONFIG_IDF_TARGET_ESP32
22 #include "esp32/rom/cache.h"
23 #elif CONFIG_IDF_TARGET_ESP32S2
24 #include "esp32s2/rom/cache.h"
25 #elif CONFIG_IDF_TARGET_ESP32S3
26 #include "esp32s3/rom/ets_sys.h"
27 #include "esp32s3/rom/cache.h"
28 #elif CONFIG_IDF_TARGET_ESP32C3
29 #include "esp32c3/rom/ets_sys.h"
30 #include "esp32c3/rom/cache.h"
31 #elif CONFIG_IDF_TARGET_ESP32H2
32 #include "esp32h2/rom/ets_sys.h"
33 #include "esp32h2/rom/cache.h"
34 #endif
35
36 #include "esp_attr.h"
37
38 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
39 typedef struct {
40 uint32_t icache_autoload;
41 uint32_t dcache_autoload;
42 } spi_noos_arg_t;
43
44 static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
45 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
46 typedef struct {
47 uint32_t icache_autoload;
48 } spi_noos_arg_t;
49
50 static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
51 #endif
52
start(void * arg)53 static IRAM_ATTR esp_err_t start(void *arg)
54 {
55 #if CONFIG_IDF_TARGET_ESP32
56 Cache_Read_Disable(0);
57 Cache_Read_Disable(1);
58 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
59 spi_noos_arg_t *spi_arg = arg;
60 spi_arg->icache_autoload = Cache_Suspend_ICache();
61 spi_arg->dcache_autoload = Cache_Suspend_DCache();
62 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
63 spi_noos_arg_t *spi_arg = arg;
64 spi_arg->icache_autoload = Cache_Suspend_ICache();
65 #endif
66 return ESP_OK;
67 }
68
end(void * arg)69 static IRAM_ATTR esp_err_t end(void *arg)
70 {
71 #if CONFIG_IDF_TARGET_ESP32
72 Cache_Flush(0);
73 Cache_Flush(1);
74 Cache_Read_Enable(0);
75 Cache_Read_Enable(1);
76 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
77 spi_noos_arg_t *spi_arg = arg;
78 Cache_Invalidate_ICache_All();
79 Cache_Resume_ICache(spi_arg->icache_autoload);
80 Cache_Resume_DCache(spi_arg->dcache_autoload);
81 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
82 spi_noos_arg_t *spi_arg = arg;
83 Cache_Invalidate_ICache_All();
84 Cache_Resume_ICache(spi_arg->icache_autoload);
85 #endif
86 return ESP_OK;
87 }
88
delay_us(void * arg,uint32_t us)89 static IRAM_ATTR esp_err_t delay_us(void *arg, uint32_t us)
90 {
91 esp_rom_delay_us(us);
92 return ESP_OK;
93 }
94
95 // Currently when the os is not up yet, the caller is supposed to call esp_flash APIs with proper
96 // buffers.
get_temp_buffer_not_supported(void * arg,size_t reqest_size,size_t * out_size)97 IRAM_ATTR void* get_temp_buffer_not_supported(void* arg, size_t reqest_size, size_t* out_size)
98 {
99 return NULL;
100 }
101
102 const DRAM_ATTR esp_flash_os_functions_t esp_flash_noos_functions = {
103 .start = start,
104 .end = end,
105 .delay_us = delay_us,
106 .region_protected = NULL,
107 /* the caller is supposed to call esp_flash_read/esp_flash_write APIs with buffers in DRAM */
108 .get_temp_buffer = NULL,
109 .release_temp_buffer = NULL,
110 .yield = NULL,
111 };
112
esp_flash_app_disable_os_functions(esp_flash_t * chip)113 esp_err_t IRAM_ATTR esp_flash_app_disable_os_functions(esp_flash_t* chip)
114 {
115 chip->os_func = &esp_flash_noos_functions;
116
117 #if !CONFIG_IDF_TARGET_ESP32
118 chip->os_func_data = &spi_arg;
119 #endif
120
121 return ESP_OK;
122 }
123
