1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #pragma once 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /*IRAM0 is connected with Cache IBUS0*/ 21 #define IRAM0_ADDRESS_LOW 0x40000000 22 #define IRAM0_ADDRESS_HIGH 0x44000000 23 #define IRAM0_CACHE_ADDRESS_LOW 0x42000000 24 #define IRAM0_CACHE_ADDRESS_HIGH 0x44000000 25 26 /*DRAM0 is connected with Cache DBUS0*/ 27 #define DRAM0_ADDRESS_LOW 0x3C000000 28 #define DRAM0_ADDRESS_HIGH 0x40000000 29 #define DRAM0_CACHE_ADDRESS_LOW 0x3C000000 30 #define DRAM0_CACHE_ADDRESS_HIGH 0x3E000000 31 #define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH 32 #define ESP_CACHE_TEMP_ADDR 0x3C800000 33 34 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) 35 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) 36 37 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) 38 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) 39 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) 40 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) 41 42 #define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) 43 #define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) 44 45 #define CACHE_IBUS 0 46 #define CACHE_IBUS_MMU_START 0 47 #define CACHE_IBUS_MMU_END 0x800 48 49 #define CACHE_DBUS 1 50 #define CACHE_DBUS_MMU_START 0 51 #define CACHE_DBUS_MMU_END 0x800 52 53 #define CACHE_IROM_MMU_START 0 54 #define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() 55 #define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) 56 57 #define CACHE_DROM_MMU_START CACHE_IROM_MMU_END 58 #define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() 59 #define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) 60 61 #define CACHE_DROM_MMU_MAX_END 0x400 62 63 #define ICACHE_MMU_SIZE 0x800 64 #define DCACHE_MMU_SIZE 0x800 65 66 #define MMU_BUS_START(i) 0 67 #define MMU_BUS_SIZE(i) 0x800 68 69 #define MMU_INVALID BIT(14) 70 #define MMU_TYPE BIT(15) 71 #define MMU_ACCESS_FLASH 0 72 #define MMU_ACCESS_SPIRAM BIT(15) 73 74 #define CACHE_MAX_SYNC_NUM 0x400000 75 #define CACHE_MAX_LOCK_NUM 0x8000 76 77 #define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) 78 #define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) 79 80 #define MMU_TABLE_INVALID_VAL 0x4000 81 #define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL 82 #define MMU_ADDRESS_MASK 0x3fff 83 #define MMU_PAGE_SIZE 0x10000 84 #define INVALID_PHY_PAGE 0xffff 85 86 #define BUS_ADDR_SIZE 0x2000000 87 #define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1) 88 89 #define CACHE_ICACHE_LOW_SHIFT 0 90 #define CACHE_ICACHE_HIGH_SHIFT 2 91 #define CACHE_DCACHE_LOW_SHIFT 4 92 #define CACHE_DCACHE_HIGH_SHIFT 6 93 94 #define CACHE_MEMORY_IBANK0_ADDR 0x40370000 95 #define CACHE_MEMORY_IBANK1_ADDR 0x40374000 96 97 #define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000 98 #define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000 99 100 #ifdef __cplusplus 101 } 102 #endif 103
