1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_ASSIST_DEBUG_REG_H_ 15 #define _SOC_ASSIST_DEBUG_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000) 23 /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 24 /*description: */ 25 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) 26 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11)) 27 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1 28 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 29 /* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 30 /*description: */ 31 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) 32 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10)) 33 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1 34 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 35 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 36 /*description: */ 37 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) 38 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (BIT(9)) 39 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x1 40 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 41 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 42 /*description: */ 43 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) 44 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (BIT(8)) 45 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x1 46 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 47 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 48 /*description: */ 49 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) 50 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (BIT(7)) 51 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x1 52 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 53 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 54 /*description: */ 55 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) 56 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6)) 57 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1 58 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 59 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 60 /*description: */ 61 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) 62 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (BIT(5)) 63 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x1 64 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 65 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 66 /*description: */ 67 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) 68 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (BIT(4)) 69 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x1 70 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 71 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 72 /*description: */ 73 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) 74 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (BIT(3)) 75 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x1 76 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 77 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 78 /*description: */ 79 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) 80 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2)) 81 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1 82 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 83 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 84 /*description: */ 85 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) 86 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (BIT(1)) 87 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x1 88 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 89 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 90 /*description: */ 91 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) 92 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (BIT(0)) 93 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x1 94 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 95 96 #define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x004) 97 /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 98 /*description: */ 99 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) 100 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11)) 101 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1 102 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 103 /* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 104 /*description: */ 105 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) 106 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10)) 107 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1 108 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 109 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 110 /*description: */ 111 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) 112 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (BIT(9)) 113 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x1 114 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 115 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 116 /*description: */ 117 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) 118 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8)) 119 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1 120 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 121 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 122 /*description: */ 123 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) 124 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (BIT(7)) 125 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x1 126 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 127 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 128 /*description: */ 129 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) 130 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (BIT(6)) 131 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x1 132 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 133 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 134 /*description: */ 135 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) 136 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (BIT(5)) 137 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x1 138 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 139 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 140 /*description: */ 141 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) 142 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4)) 143 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1 144 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 145 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 146 /*description: */ 147 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) 148 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (BIT(3)) 149 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x1 150 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 151 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 152 /*description: */ 153 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) 154 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (BIT(2)) 155 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x1 156 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 157 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 158 /*description: */ 159 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) 160 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (BIT(1)) 161 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x1 162 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 163 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 164 /*description: */ 165 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) 166 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0)) 167 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1 168 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 169 170 #define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x008) 171 /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */ 172 /*description: */ 173 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) 174 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11)) 175 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1 176 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11 177 /* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */ 178 /*description: */ 179 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) 180 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10)) 181 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1 182 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 183 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */ 184 /*description: */ 185 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9)) 186 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9)) 187 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1 188 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9 189 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */ 190 /*description: */ 191 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8)) 192 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (BIT(8)) 193 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x1 194 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8 195 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */ 196 /*description: */ 197 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7)) 198 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (BIT(7)) 199 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x1 200 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7 201 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */ 202 /*description: */ 203 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6)) 204 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (BIT(6)) 205 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x1 206 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6 207 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */ 208 /*description: */ 209 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5)) 210 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5)) 211 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1 212 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5 213 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */ 214 /*description: */ 215 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4)) 216 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (BIT(4)) 217 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x1 218 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4 219 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */ 220 /*description: */ 221 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3)) 222 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (BIT(3)) 223 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x1 224 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3 225 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */ 226 /*description: */ 227 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2)) 228 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (BIT(2)) 229 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x1 230 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2 231 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */ 232 /*description: */ 233 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1)) 234 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1)) 235 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1 236 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1 237 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 238 /*description: */ 239 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0)) 240 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (BIT(0)) 241 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x1 242 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0 243 244 #define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x00C) 245 /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */ 246 /*description: */ 247 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) 248 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11)) 249 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1 250 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 251 /* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */ 252 /*description: */ 253 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) 254 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10)) 255 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1 256 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 257 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */ 258 /*description: */ 259 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) 260 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (BIT(9)) 261 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x1 262 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 263 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ 264 /*description: */ 265 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) 266 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (BIT(8)) 267 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x1 268 #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 269 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ 270 /*description: */ 271 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) 272 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (BIT(7)) 273 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x1 274 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 275 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ 276 /*description: */ 277 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) 278 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6)) 279 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1 280 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 281 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ 282 /*description: */ 283 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) 284 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (BIT(5)) 285 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x1 286 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 287 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ 288 /*description: */ 289 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) 290 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (BIT(4)) 291 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x1 292 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 293 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ 294 /*description: */ 295 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) 296 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (BIT(3)) 297 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x1 298 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 299 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ 300 /*description: */ 301 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) 302 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2)) 303 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1 304 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 305 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ 306 /*description: */ 307 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) 308 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (BIT(1)) 309 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x1 310 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 311 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 312 /*description: */ 313 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) 314 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (BIT(0)) 315 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x1 316 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 317 318 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x010) 319 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ 320 /*description: */ 321 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF 322 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)) 323 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF 324 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 325 326 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x014) 327 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 328 /*description: */ 329 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFF 330 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)) 331 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFF 332 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 333 334 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x018) 335 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ 336 /*description: */ 337 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFF 338 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)) 339 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFF 340 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 341 342 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x01C) 343 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 344 /*description: */ 345 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF 346 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)) 347 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF 348 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 349 350 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x020) 351 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ 352 /*description: */ 353 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFF 354 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)) 355 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFF 356 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 357 358 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x024) 359 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 360 /*description: */ 361 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFF 362 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)) 363 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFF 364 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 365 366 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x028) 367 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ 368 /*description: */ 369 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF 370 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)) 371 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF 372 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 373 374 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x02C) 375 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 376 /*description: */ 377 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFF 378 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)) 379 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFF 380 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 381 382 #define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x030) 383 /* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 384 /*description: */ 385 #define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF 386 #define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S)) 387 #define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF 388 #define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 389 390 #define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x034) 391 /* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 392 /*description: */ 393 #define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFF 394 #define ASSIST_DEBUG_CORE_0_AREA_SP_M ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S)) 395 #define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFF 396 #define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 397 398 #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x038) 399 /* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */ 400 /*description: */ 401 #define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFF 402 #define ASSIST_DEBUG_CORE_0_SP_MIN_M ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S)) 403 #define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFF 404 #define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 405 406 #define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x03C) 407 /* ASSIST_DEBUG_CORE_0_SP_MAX : RW ;bitpos:[31:0] ;default: ~32'b0 ; */ 408 /*description: */ 409 #define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF 410 #define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S)) 411 #define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF 412 #define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 413 414 #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x040) 415 /* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 416 /*description: */ 417 #define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFF 418 #define ASSIST_DEBUG_CORE_0_SP_PC_M ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S)) 419 #define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFF 420 #define ASSIST_DEBUG_CORE_0_SP_PC_S 0 421 422 #define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x044) 423 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */ 424 /*description: enable CPU Pdebug function if enable CPU will update PdebugPC*/ 425 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) 426 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (BIT(1)) 427 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x1 428 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 429 /* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */ 430 /*description: enable recording function if enable assist_debug will update 431 PdebugPC so you can read it*/ 432 #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) 433 #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (BIT(0)) 434 #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x1 435 #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 436 437 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x048) 438 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 439 /*description: */ 440 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFF 441 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)) 442 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFF 443 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 444 445 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x04C) 446 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 447 /*description: */ 448 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFF 449 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)) 450 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFF 451 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 452 453 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x050) 454 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */ 455 /*description: */ 456 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) 457 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25)) 458 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1 459 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25 460 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ 461 /*description: */ 462 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24)) 463 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (BIT(24)) 464 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x1 465 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24 466 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ 467 /*description: */ 468 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFF 469 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)) 470 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF 471 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 472 473 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x054) 474 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */ 475 /*description: */ 476 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) 477 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25)) 478 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1 479 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25 480 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ 481 /*description: */ 482 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24)) 483 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (BIT(24)) 484 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x1 485 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24 486 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ 487 /*description: */ 488 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFF 489 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)) 490 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF 491 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 492 493 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x058) 494 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */ 495 /*description: */ 496 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000F 497 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)) 498 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0xF 499 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25 500 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ 501 /*description: */ 502 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24)) 503 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(24)) 504 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1 505 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24 506 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ 507 /*description: */ 508 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFF 509 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)) 510 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0xFFFFFF 511 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 512 513 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x05C) 514 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 515 /*description: */ 516 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF 517 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)) 518 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF 519 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 520 521 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x060) 522 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */ 523 /*description: */ 524 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000F 525 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)) 526 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xF 527 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25 528 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ 529 /*description: */ 530 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24)) 531 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (BIT(24)) 532 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x1 533 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24 534 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ 535 /*description: */ 536 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFF 537 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)) 538 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0xFFFFFF 539 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 540 541 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x064) 542 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 543 /*description: */ 544 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFF 545 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)) 546 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF 547 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 548 549 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x068) 550 /* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ 551 /*description: */ 552 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF 553 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)) 554 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF 555 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 556 557 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x06C) 558 /* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ 559 /*description: */ 560 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFF 561 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)) 562 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0xFFFFF 563 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 564 565 #define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x070) 566 /* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */ 567 /*description: */ 568 #define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7)) 569 #define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(7)) 570 #define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1 571 #define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7 572 /* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */ 573 /*description: */ 574 #define ASSIST_DEBUG_LOG_MODE 0x0000000F 575 #define ASSIST_DEBUG_LOG_MODE_M ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S)) 576 #define ASSIST_DEBUG_LOG_MODE_V 0xF 577 #define ASSIST_DEBUG_LOG_MODE_S 3 578 /* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 579 /*description: */ 580 #define ASSIST_DEBUG_LOG_ENA 0x00000007 581 #define ASSIST_DEBUG_LOG_ENA_M ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S)) 582 #define ASSIST_DEBUG_LOG_ENA_V 0x7 583 #define ASSIST_DEBUG_LOG_ENA_S 0 584 585 #define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x074) 586 /* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 587 /*description: */ 588 #define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFF 589 #define ASSIST_DEBUG_LOG_DATA_0_M ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S)) 590 #define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFF 591 #define ASSIST_DEBUG_LOG_DATA_0_S 0 592 593 #define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x078) 594 /* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ 595 /*description: */ 596 #define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF 597 #define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S)) 598 #define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF 599 #define ASSIST_DEBUG_LOG_DATA_SIZE_S 0 600 601 #define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x07C) 602 /* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 603 /*description: */ 604 #define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFF 605 #define ASSIST_DEBUG_LOG_MIN_M ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S)) 606 #define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFF 607 #define ASSIST_DEBUG_LOG_MIN_S 0 608 609 #define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x080) 610 /* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 611 /*description: */ 612 #define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFF 613 #define ASSIST_DEBUG_LOG_MAX_M ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S)) 614 #define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFF 615 #define ASSIST_DEBUG_LOG_MAX_S 0 616 617 #define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x084) 618 /* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 619 /*description: */ 620 #define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF 621 #define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S)) 622 #define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF 623 #define ASSIST_DEBUG_LOG_MEM_START_S 0 624 625 #define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x088) 626 /* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 627 /*description: */ 628 #define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFF 629 #define ASSIST_DEBUG_LOG_MEM_END_M ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S)) 630 #define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFF 631 #define ASSIST_DEBUG_LOG_MEM_END_S 0 632 633 #define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x08C) 634 /* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 635 /*description: */ 636 #define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFF 637 #define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S)) 638 #define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFF 639 #define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0 640 641 #define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x090) 642 /* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */ 643 /*description: */ 644 #define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1)) 645 #define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (BIT(1)) 646 #define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x1 647 #define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1 648 /* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ 649 /*description: */ 650 #define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0)) 651 #define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0)) 652 #define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1 653 #define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0 654 655 #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x094) 656 /* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 657 /*description: */ 658 #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFF 659 #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)) 660 #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFF 661 #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 662 663 #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x098) 664 /* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */ 665 /*description: */ 666 #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) 667 #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (BIT(1)) 668 #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x1 669 #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 670 /* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ 671 /*description: */ 672 #define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) 673 #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (BIT(0)) 674 #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x1 675 #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 676 677 #define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC) 678 /* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */ 679 /*description: */ 680 #define ASSIST_DEBUG_DATE 0x0FFFFFFF 681 #define ASSIST_DEBUG_DATE_M ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S)) 682 #define ASSIST_DEBUG_DATE_V 0xFFFFFFF 683 #define ASSIST_DEBUG_DATE_S 0 684 685 #ifdef __cplusplus 686 } 687 #endif 688 689 690 691 #endif /*_SOC_ASSIST_DEBUG_REG_H_ */ 692
