1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SENS_STRUCT_H_ 15 #define _SOC_SENS_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct sens_dev_s { 24 union { 25 struct { 26 uint32_t sar1_clk_div: 8; 27 uint32_t sar1_sample_cycle: 8; 28 uint32_t sar1_sample_bit: 2; 29 uint32_t sar1_clk_gated: 1; 30 uint32_t sar1_sample_num: 8; 31 uint32_t sar1_dig_force: 1; /*1: ADC1 is controlled by the digital controller 0: RTC controller*/ 32 uint32_t sar1_data_inv: 1; 33 uint32_t reserved29: 3; 34 }; 35 uint32_t val; 36 } sar_read_ctrl; 37 uint32_t sar_read_status1; /**/ 38 union { 39 struct { 40 uint32_t sar_amp_wait1:16; 41 uint32_t sar_amp_wait2:16; 42 }; 43 uint32_t val; 44 } sar_meas_wait1; 45 union { 46 struct { 47 uint32_t sar_amp_wait3: 16; 48 uint32_t force_xpd_amp: 2; 49 uint32_t force_xpd_sar: 2; 50 uint32_t sar2_rstb_wait: 8; 51 uint32_t reserved28: 4; 52 }; 53 uint32_t val; 54 } sar_meas_wait2; 55 union { 56 struct { 57 uint32_t xpd_sar_amp_fsm: 4; 58 uint32_t amp_rst_fb_fsm: 4; 59 uint32_t amp_short_ref_fsm: 4; 60 uint32_t amp_short_ref_gnd_fsm: 4; 61 uint32_t xpd_sar_fsm: 4; 62 uint32_t sar_rstb_fsm: 4; 63 uint32_t sar2_xpd_wait: 8; 64 }; 65 uint32_t val; 66 } sar_meas_ctrl; 67 uint32_t sar_read_status2; /**/ 68 uint32_t ulp_cp_sleep_cyc0; /**/ 69 uint32_t ulp_cp_sleep_cyc1; /**/ 70 uint32_t ulp_cp_sleep_cyc2; /**/ 71 uint32_t ulp_cp_sleep_cyc3; /**/ 72 uint32_t ulp_cp_sleep_cyc4; /**/ 73 union { 74 struct { 75 uint32_t sar1_bit_width: 2; 76 uint32_t sar2_bit_width: 2; 77 uint32_t sar2_en_test: 1; 78 uint32_t sar2_pwdet_cct: 3; 79 uint32_t ulp_cp_force_start_top: 1; 80 uint32_t ulp_cp_start_top: 1; 81 uint32_t sarclk_en: 1; 82 uint32_t pc_init: 11; 83 uint32_t sar2_stop: 1; 84 uint32_t sar1_stop: 1; 85 uint32_t sar2_pwdet_en: 1; 86 uint32_t reserved25: 7; 87 }; 88 uint32_t val; 89 } sar_start_force; 90 union { 91 struct { 92 uint32_t mem_wr_addr_init: 11; 93 uint32_t mem_wr_addr_size: 11; 94 uint32_t rtc_mem_wr_offst_clr: 1; 95 uint32_t reserved23: 9; 96 }; 97 uint32_t val; 98 } sar_mem_wr_ctrl; 99 uint32_t sar_atten1; /**/ 100 uint32_t sar_atten2; /**/ 101 union { 102 struct { 103 uint32_t i2c_slave_addr1: 11; 104 uint32_t i2c_slave_addr0: 11; 105 uint32_t meas_status: 8; 106 uint32_t reserved30: 2; 107 }; 108 uint32_t val; 109 } sar_slave_addr1; 110 union { 111 struct { 112 uint32_t i2c_slave_addr3:11; 113 uint32_t i2c_slave_addr2:11; 114 uint32_t reserved22: 10; 115 }; 116 uint32_t val; 117 } sar_slave_addr2; 118 union { 119 struct { 120 uint32_t i2c_slave_addr5:11; 121 uint32_t i2c_slave_addr4:11; 122 uint32_t tsens_out: 8; 123 uint32_t tsens_rdy_out: 1; 124 uint32_t reserved31: 1; 125 }; 126 uint32_t val; 127 } sar_slave_addr3; 128 union { 129 struct { 130 uint32_t i2c_slave_addr7:11; 131 uint32_t i2c_slave_addr6:11; 132 uint32_t i2c_rdata: 8; 133 uint32_t i2c_done: 1; 134 uint32_t reserved31: 1; 135 }; 136 uint32_t val; 137 } sar_slave_addr4; 138 union { 139 struct { 140 uint32_t tsens_xpd_wait: 12; 141 uint32_t tsens_xpd_force: 1; 142 uint32_t tsens_clk_inv: 1; 143 uint32_t tsens_clk_gated: 1; 144 uint32_t tsens_in_inv: 1; 145 uint32_t tsens_clk_div: 8; 146 uint32_t tsens_power_up: 1; 147 uint32_t tsens_power_up_force: 1; 148 uint32_t tsens_dump_out: 1; 149 uint32_t reserved27: 5; 150 }; 151 uint32_t val; 152 } sar_tctrl; 153 union { 154 struct { 155 uint32_t sar_i2c_ctrl: 28; 156 uint32_t sar_i2c_start: 1; 157 uint32_t sar_i2c_start_force: 1; 158 uint32_t reserved30: 2; 159 }; 160 uint32_t val; 161 } sar_i2c_ctrl; 162 union { 163 struct { 164 uint32_t meas1_data_sar: 16; 165 uint32_t meas1_done_sar: 1; 166 uint32_t meas1_start_sar: 1; 167 uint32_t meas1_start_force: 1; /*1: ADC1 is controlled by the digital or RTC controller 0: Ulp coprocessor*/ 168 uint32_t sar1_en_pad: 12; 169 uint32_t sar1_en_pad_force: 1; /*1: Data ports are controlled by the digital or RTC controller 0: Ulp coprocessor*/ 170 }; 171 uint32_t val; 172 } sar_meas_start1; 173 union { 174 struct { 175 uint32_t touch_meas_delay:16; 176 uint32_t touch_xpd_wait: 8; 177 uint32_t touch_out_sel: 1; 178 uint32_t touch_out_1en: 1; 179 uint32_t xpd_hall_force: 1; /*1: Power of hall sensor is controlled by the digital or RTC controller 0: Ulp coprocessor*/ 180 uint32_t hall_phase_force: 1; /*1: Phase of hall sensor is controlled by the digital or RTC controller 0: Ulp coprocessor*/ 181 uint32_t reserved28: 4; 182 }; 183 uint32_t val; 184 } sar_touch_ctrl1; 185 union { 186 struct { 187 uint32_t l_thresh: 16; 188 uint32_t h_thresh: 16; 189 }; 190 uint32_t val; 191 } touch_thresh[5]; 192 union { 193 struct { 194 uint32_t l_val: 16; 195 uint32_t h_val: 16; 196 }; 197 uint32_t val; 198 } touch_meas[5]; 199 union { 200 struct { 201 uint32_t touch_meas_en: 10; 202 uint32_t touch_meas_done: 1; 203 uint32_t touch_start_fsm_en: 1; 204 uint32_t touch_start_en: 1; 205 uint32_t touch_start_force: 1; 206 uint32_t touch_sleep_cycles:16; 207 uint32_t touch_meas_en_clr: 1; 208 uint32_t reserved31: 1; 209 }; 210 uint32_t val; 211 } sar_touch_ctrl2; 212 uint32_t reserved_88; 213 union { 214 struct { 215 uint32_t touch_pad_worken:10; 216 uint32_t touch_pad_outen2:10; 217 uint32_t touch_pad_outen1:10; 218 uint32_t reserved30: 2; 219 }; 220 uint32_t val; 221 } sar_touch_enable; 222 union { 223 struct { 224 uint32_t sar2_clk_div: 8; 225 uint32_t sar2_sample_cycle: 8; 226 uint32_t sar2_sample_bit: 2; 227 uint32_t sar2_clk_gated: 1; 228 uint32_t sar2_sample_num: 8; 229 uint32_t sar2_pwdet_force: 1; /*1: ADC2 is controlled by PWDET 0: digital or RTC controller*/ 230 uint32_t sar2_dig_force: 1; /*1: ADC2 is controlled by the digital controller 0: RTC controller*/ 231 uint32_t sar2_data_inv: 1; 232 uint32_t reserved30: 2; 233 }; 234 uint32_t val; 235 } sar_read_ctrl2; 236 union { 237 struct { 238 uint32_t meas2_data_sar: 16; 239 uint32_t meas2_done_sar: 1; 240 uint32_t meas2_start_sar: 1; 241 uint32_t meas2_start_force: 1; /*1: ADC2 is controlled by the digital or RTC controller 0: Ulp coprocessor*/ 242 uint32_t sar2_en_pad: 12; 243 uint32_t sar2_en_pad_force: 1; /*1: Data ports are controlled by the digital or RTC controller 0: Ulp coprocessor*/ 244 }; 245 uint32_t val; 246 } sar_meas_start2; 247 union { 248 struct { 249 uint32_t sw_fstep: 16; 250 uint32_t sw_tone_en: 1; 251 uint32_t debug_bit_sel: 5; 252 uint32_t dac_dig_force: 1; 253 uint32_t dac_clk_force_low: 1; 254 uint32_t dac_clk_force_high: 1; 255 uint32_t dac_clk_inv: 1; 256 uint32_t reserved26: 6; 257 }; 258 uint32_t val; 259 } sar_dac_ctrl1; 260 union { 261 struct { 262 uint32_t dac_dc1: 8; 263 uint32_t dac_dc2: 8; 264 uint32_t dac_scale1: 2; 265 uint32_t dac_scale2: 2; 266 uint32_t dac_inv1: 2; 267 uint32_t dac_inv2: 2; 268 uint32_t dac_cw_en1: 1; 269 uint32_t dac_cw_en2: 1; 270 uint32_t reserved26: 6; 271 }; 272 uint32_t val; 273 } sar_dac_ctrl2; 274 union { 275 struct { 276 uint32_t sar1_dac_xpd_fsm: 4; 277 uint32_t sar1_dac_xpd_fsm_idle: 1; 278 uint32_t xpd_sar_amp_fsm_idle: 1; 279 uint32_t amp_rst_fb_fsm_idle: 1; 280 uint32_t amp_short_ref_fsm_idle: 1; 281 uint32_t amp_short_ref_gnd_fsm_idle: 1; 282 uint32_t xpd_sar_fsm_idle: 1; 283 uint32_t sar_rstb_fsm_idle: 1; 284 uint32_t sar2_rstb_force: 2; 285 uint32_t amp_rst_fb_force: 2; 286 uint32_t amp_short_ref_force: 2; 287 uint32_t amp_short_ref_gnd_force: 2; 288 uint32_t reserved19: 13; 289 }; 290 uint32_t val; 291 } sar_meas_ctrl2; 292 uint32_t reserved_a4; 293 uint32_t reserved_a8; 294 uint32_t reserved_ac; 295 uint32_t reserved_b0; 296 uint32_t reserved_b4; 297 uint32_t reserved_b8; 298 uint32_t reserved_bc; 299 uint32_t reserved_c0; 300 uint32_t reserved_c4; 301 uint32_t reserved_c8; 302 uint32_t reserved_cc; 303 uint32_t reserved_d0; 304 uint32_t reserved_d4; 305 uint32_t reserved_d8; 306 uint32_t reserved_dc; 307 uint32_t reserved_e0; 308 uint32_t reserved_e4; 309 uint32_t reserved_e8; 310 uint32_t reserved_ec; 311 uint32_t reserved_f0; 312 uint32_t reserved_f4; 313 uint32_t sar_nouse; /**/ 314 union { 315 struct { 316 uint32_t sar_date: 28; 317 uint32_t reserved28: 4; 318 }; 319 uint32_t val; 320 } sardate; 321 } sens_dev_t; 322 extern sens_dev_t SENS; 323 324 #ifdef __cplusplus 325 } 326 #endif 327 328 #endif /* _SOC_SENS_STRUCT_H_ */ 329
