1 /* 2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef BOOTLOADER_BUILD 8 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include "sdkconfig.h" 12 #include "esp_attr.h" 13 #include "soc/soc.h" 14 #include "soc/dport_reg.h" 15 #include "soc/tracemem_config.h" 16 #include "heap_memory_layout.h" 17 #include "esp_heap_caps.h" 18 19 /** 20 * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. 21 * Each type of memory map consists of one or more regions in the address space. 22 * Each type contains an array of prioritized capabilities. 23 * Types with later entries are only taken if earlier ones can't fulfill the memory request. 24 * 25 * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. 26 * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. 27 * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. 28 * - Most other malloc caps only fit in one region anyway. 29 * 30 */ 31 const soc_memory_type_desc_t soc_memory_types[] = { 32 // Type 0: DRAM 33 { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, 34 // Type 1: DRAM used for startup stacks 35 { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true}, 36 // Type 2: DRAM which has an alias on the I-port 37 { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, 38 // Type 3: IRAM 39 { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, 40 // Type 4: SPI SRAM data 41 { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false}, 42 // Type 5: DRAM which is not DMA accesible 43 { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false}, 44 // Type 6: RTC Fast RAM 45 { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, 46 }; 47 48 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); 49 50 /** 51 * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. 52 * 53 * @note Because of requirements in the coalescing code which merges adjacent regions, 54 * this list should always be sorted from low to high by start address. 55 * 56 */ 57 const soc_memory_region_t soc_memory_regions[] = { 58 #ifdef CONFIG_SPIRAM 59 { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available 60 #endif 61 #if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB 62 { 0x40374000, 0x4000, 3, 0}, //Level 1, IRAM 63 #endif 64 { 0x3FC88000, 0x8000, 2, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy 65 { 0x3FC90000, 0x10000, 2, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy 66 { 0x3FCA0000, 0x10000, 2, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy 67 { 0x3FCB0000, 0x10000, 2, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy 68 { 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy 69 { 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy 70 { 0x3FCE0000, 0x10000, 1, 0}, //Level 8, IDRAM, can be used as trace memroy, contains stacks used by startup flow, recycled by heap allocator in app_main task 71 #if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB 72 { 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM 73 #endif 74 #if CONFIG_ESP32S3_DATA_CACHE_16KB 75 { 0x3C000000, 0x4000, 5, 0} 76 #endif 77 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 78 { 0x600fe000, 0x2000, 6, 0}, //Fast RTC memory 79 #endif 80 }; 81 82 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); 83 84 extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end; // defined in sections.ld.in 85 86 /** 87 * Reserved memory regions. 88 * These are removed from the soc_memory_regions array when heaps are created. 89 * 90 */ 91 92 // Static data region. DRAM used by data+bss and possibly rodata 93 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); 94 95 // ESP32S3 has a big D/IRAM region, the part used by code is reserved 96 // The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address 97 #define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) 98 // .text region in diram. DRAM used by text (shared with IBUS). 99 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); 100 101 #if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB 102 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code_2); 103 #endif 104 105 #ifdef CONFIG_SPIRAM 106 /* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this 107 * memory to heap depending on the actual SPIRAM chip size. */ 108 SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region); 109 #endif 110 111 #if CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM > 0 112 SOC_RESERVE_MEMORY_REGION(TRACEMEM_BLK0_ADDR, TRACEMEM_BLK0_ADDR + CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM / 2, trace_mem0); 113 SOC_RESERVE_MEMORY_REGION(TRACEMEM_BLK1_ADDR, TRACEMEM_BLK1_ADDR + CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM / 2, trace_mem1); 114 #endif 115 116 // RTC Fast RAM region 117 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 118 #ifdef CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM 119 SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data); 120 #else 121 SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data); 122 #endif 123 #endif 124 125 #endif // BOOTLOADER_BUILD 126
