1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #pragma once
16
17 #include <zephyr/kernel.h>
18 #include <stdint.h>
19 #include "soc/soc_caps.h"
20 #include "soc/soc.h"
21 #include "xtensa/xtensa_api.h"
22 #include "xtensa/config/specreg.h"
23 #include "xt_instr_macros.h"
24
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28
29 /**
30 * @brief enable interrupts specified by the mask
31 *
32 * @param mask bitmask of interrupts that needs to be enabled
33 */
intr_cntrl_ll_enable_interrupts(uint32_t mask)34 static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask)
35 {
36 #ifdef __ZEPHYR__
37 z_xt_ints_on(mask);
38 #else
39 xt_ints_on(mask);
40 #endif
41 }
42
43 /**
44 * @brief disable interrupts specified by the mask
45 *
46 * @param mask bitmask of interrupts that needs to be disabled
47 */
intr_cntrl_ll_disable_interrupts(uint32_t mask)48 static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
49 {
50 #ifdef __ZEPHYR__
51 z_xt_ints_off(mask);
52 #else
53 xt_ints_off(mask);
54 #endif
55 }
56
57 /**
58 * @brief Read the current interrupt mask of the CPU running this code.
59 *
60 * @return The current interrupt bitmask.
61 */
intr_cntrl_ll_read_interrupt_mask(void)62 static inline uint32_t intr_cntrl_ll_read_interrupt_mask(void)
63 {
64 uint32_t int_mask;
65 RSR(INTENABLE, int_mask);
66 return int_mask;
67 }
68
69 /**
70 * @brief checks if given interrupt number has a valid handler
71 *
72 * @param intr interrupt number ranged from 0 to 31
73 * @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
74 * @return true for valid handler, false otherwise
75 */
intr_cntrl_ll_has_handler(uint8_t intr,uint8_t cpu)76 static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
77 {
78 return xt_int_has_handler(intr, cpu);
79 }
80
81 /**
82 * @brief sets interrupt handler and optional argument of a given interrupt number
83 *
84 * @param intr interrupt number ranged from 0 to 31
85 * @param handler handler invoked when an interrupt occurs
86 * @param arg optional argument to pass to the handler
87 */
intr_cntrl_ll_set_int_handler(uint8_t intr,interrupt_handler_t handler,void * arg)88 static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
89 {
90 xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
91 }
92
93 /**
94 * @brief Gets argument passed to handler of a given interrupt number
95 *
96 * @param intr interrupt number ranged from 0 to 31
97 *
98 * @return argument used by handler of passed interrupt number
99 */
intr_cntrl_ll_get_int_handler_arg(uint8_t intr)100 static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
101 {
102 return xt_get_interrupt_handler_arg(intr);
103 }
104
105 /**
106 * @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
107 *
108 * @param intr interrupt number ranged from 0 to 31
109 */
intr_cntrl_ll_edge_int_acknowledge(int intr)110 static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
111 {
112 xthal_set_intclear(1 << intr);
113 }
114 #ifdef __cplusplus
115 }
116 #endif
117
