1# This file describes eFuses fields and registers for ESP32-C3 chip 2# 3# SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 4# 5# SPDX-License-Identifier: GPL-2.0-or-later 6 7from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase 8 9 10# fmt: off 11class EfuseDefineRegisters(EfuseRegistersBase): 12 13 EFUSE_MEM_SIZE = (0x01FC + 4) 14 15 # EFUSE registers & command/conf values 16 DR_REG_EFUSE_BASE = 0x60008800 17 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 18 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 19 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 20 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 21 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 22 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 23 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 24 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 25 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C 26 EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 27 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 28 EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188 29 EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C 30 EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 31 EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC 32 EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 33 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 34 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC 35 EFUSE_WRITE_OP_CODE = 0x5A5A 36 EFUSE_READ_OP_CODE = 0x5AA5 37 EFUSE_PGM_CMD_MASK = 0x3 38 EFUSE_PGM_CMD = 0x2 39 EFUSE_READ_CMD = 0x1 40 41 # this chip has a design error so fail_bit is shifted by one block but err_num is in the correct place 42 BLOCK_FAIL_BIT = [ 43 # error_reg, fail_bit 44 (EFUSE_RD_REPEAT_ERR0_REG, None), # BLOCK0 45 (EFUSE_RD_RS_ERR0_REG, 7), # MAC_SPI_8M_0 46 (EFUSE_RD_RS_ERR0_REG, 11), # BLOCK_SYS_DATA 47 (EFUSE_RD_RS_ERR0_REG, 15), # BLOCK_USR_DATA 48 (EFUSE_RD_RS_ERR0_REG, 19), # BLOCK_KEY0 49 (EFUSE_RD_RS_ERR0_REG, 23), # BLOCK_KEY1 50 (EFUSE_RD_RS_ERR0_REG, 27), # BLOCK_KEY2 51 (EFUSE_RD_RS_ERR0_REG, 31), # BLOCK_KEY3 52 (EFUSE_RD_RS_ERR1_REG, 3), # BLOCK_KEY4 53 (EFUSE_RD_RS_ERR1_REG, 7), # BLOCK_KEY5 54 (EFUSE_RD_RS_ERR1_REG, None), # BLOCK_SYS_DATA2 55 ] 56 57 BLOCK_NUM_ERRORS = [ 58 # error_reg, err_num_mask, err_num_offs 59 (EFUSE_RD_REPEAT_ERR0_REG, None, None), # BLOCK0 60 (EFUSE_RD_RS_ERR0_REG, 0x7, 0), # MAC_SPI_8M_0 61 (EFUSE_RD_RS_ERR0_REG, 0x7, 4), # BLOCK_SYS_DATA 62 (EFUSE_RD_RS_ERR0_REG, 0x7, 8), # BLOCK_USR_DATA 63 (EFUSE_RD_RS_ERR0_REG, 0x7, 12), # BLOCK_KEY0 64 (EFUSE_RD_RS_ERR0_REG, 0x7, 16), # BLOCK_KEY1 65 (EFUSE_RD_RS_ERR0_REG, 0x7, 20), # BLOCK_KEY2 66 (EFUSE_RD_RS_ERR0_REG, 0x7, 24), # BLOCK_KEY3 67 (EFUSE_RD_RS_ERR0_REG, 0x7, 28), # BLOCK_KEY4 68 (EFUSE_RD_RS_ERR1_REG, 0x7, 0), # BLOCK_KEY5 69 (EFUSE_RD_RS_ERR1_REG, 0x7, 4), # BLOCK_SYS_DATA2 70 ] 71 72 # EFUSE_WR_TIM_CONF2_REG 73 EFUSE_PWR_OFF_NUM_S = 0 74 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S 75 76 77class EfuseDefineBlocks(EfuseBlocksBase): 78 79 __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE 80 __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG 81 # List of efuse blocks 82 BLOCKS = [ 83 # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose 84 ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), 85 ("MAC_SPI_8M_0", ["BLOCK1"], 1, __base_rd_regs + 0x044, __base_wr_regs, 20, None, 6, None), 86 ("BLOCK_SYS_DATA", ["BLOCK2"], 2, __base_rd_regs + 0x05C, __base_wr_regs, 21, None, 8, None), 87 ("BLOCK_USR_DATA", ["BLOCK3"], 3, __base_rd_regs + 0x07C, __base_wr_regs, 22, None, 8, None), 88 ("BLOCK_KEY0", ["BLOCK4"], 4, __base_rd_regs + 0x09C, __base_wr_regs, 23, 0, 8, "KEY_PURPOSE_0"), 89 ("BLOCK_KEY1", ["BLOCK5"], 5, __base_rd_regs + 0x0BC, __base_wr_regs, 24, 1, 8, "KEY_PURPOSE_1"), 90 ("BLOCK_KEY2", ["BLOCK6"], 6, __base_rd_regs + 0x0DC, __base_wr_regs, 25, 2, 8, "KEY_PURPOSE_2"), 91 ("BLOCK_KEY3", ["BLOCK7"], 7, __base_rd_regs + 0x0FC, __base_wr_regs, 26, 3, 8, "KEY_PURPOSE_3"), 92 ("BLOCK_KEY4", ["BLOCK8"], 8, __base_rd_regs + 0x11C, __base_wr_regs, 27, 4, 8, "KEY_PURPOSE_4"), 93 ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), 94 ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), 95 ] 96 97 def get_burn_block_data_names(self): 98 list_of_names = [] 99 for block in self.BLOCKS: 100 blk = self.get(block) 101 if blk.name: 102 list_of_names.append(blk.name) 103 if blk.alias: 104 for alias in blk.alias: 105 list_of_names.append(alias) 106 return list_of_names 107 108 109class EfuseDefineFields(EfuseFieldsBase): 110 111 # List of efuse fields from TRM the chapter eFuse Controller. 112 EFUSES = [ 113 # 114 # Table 51: Parameters in BLOCK0 115 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 116 ("WR_DIS", "efuse", 0, 0, 0, "uint:32", None, None, None, "Disables programming of individual eFuses", None), 117 ("RD_DIS", "efuse", 0, 1, 0, "uint:7", 0, None, None, "Disables software reading from BLOCK4-10", None), 118 ("DIS_ICACHE", "config", 0, 1, 8, "bool", 2, None, None, "Disables ICache", None), 119 ("DIS_USB_JTAG", "usb config", 0, 1, 9, "bool", 2, None, None, "Disables USB JTAG. " 120 "JTAG access via pads is controlled separately", None), 121 ("DIS_DOWNLOAD_ICACHE", "config", 0, 1, 10, "bool", 2, None, None, "Disables Icache when SoC is in Download mode", None), 122 ("DIS_USB_DEVICE", "usb config", 0, 1, 11, "bool", 2, None, None, "Disables USB DEVICE", None), 123 ("DIS_FORCE_DOWNLOAD", "config", 0, 1, 12, "bool", 2, None, None, "Disables forcing chip into Download mode", None), 124 ("DIS_CAN", "config", 0, 1, 14, "bool", 2, None, None, "Disables the TWAI Controller hardware", None), 125 ("SOFT_DIS_JTAG", "jtag config", 0, 1, 16, "uint:3", 2, None, None, "Software disables JTAG. When software disabled, " 126 "JTAG can be activated temporarily by HMAC peripheral", 127 None), 128 ("DIS_PAD_JTAG", "jtag config", 0, 1, 19, "bool", 2, None, None, "Permanently disable JTAG access via pads. " 129 "USB JTAG is controlled separately.", None), 130 ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 20, "bool", 2, None, None, "Disables flash encryption when in download boot modes", 131 None), 132 ("USB_EXCHG_PINS", "usb config", 0, 1, 25, "bool", 30, None, None, "Exchanges USB D+ and D- pins", None), 133 ("VDD_SPI_AS_GPIO", "config", 0, 1, 26, "bool", 30, None, None, "Set this bit to vdd spi pin function as gpio", None), 134 ("BTLC_GPIO_ENABLE", "config", 0, 1, 27, "uint:2", 30, None, None, "Enable btlc gpio", None), 135 ("POWERGLITCH_EN", "config", 0, 1, 29, "bool", 30, None, None, "Set this bit to enable power glitch function", None), 136 ("POWER_GLITCH_DSENSE", "config", 0, 1, 30, "uint:2", 30, None, None, "Sample delay configuration of power glitch", None), 137 ("WDT_DELAY_SEL", "WDT config", 0, 2, 16, "bool", 3, None, None, "Selects RTC WDT timeout threshold at startup", None), 138 ("SPI_BOOT_CRYPT_CNT", "security", 0, 2, 18, "uint:3", 4, None, "bitcount", "Enables encryption and decryption, when an SPI boot " 139 "mode is set. Enabled when 1 or 3 bits are set," 140 "disabled otherwise", 141 {0: "Disable", 142 1: "Enable", 143 3: "Disable", 144 7: "Enable"}), 145 ("SECURE_BOOT_KEY_REVOKE0", "security", 0, 2, 21, "bool", 5, None, None, "If set, revokes use of secure boot key digest 0", None), 146 ("SECURE_BOOT_KEY_REVOKE1", "security", 0, 2, 22, "bool", 6, None, None, "If set, revokes use of secure boot key digest 1", None), 147 ("SECURE_BOOT_KEY_REVOKE2", "security", 0, 2, 23, "bool", 7, None, None, "If set, revokes use of secure boot key digest 2", None), 148 ("KEY_PURPOSE_0", "security", 0, 2, 24, "uint:4", 8, None, "keypurpose", "KEY0 purpose", None), 149 ("KEY_PURPOSE_1", "security", 0, 2, 28, "uint:4", 9, None, "keypurpose", "KEY1 purpose", None), 150 ("KEY_PURPOSE_2", "security", 0, 3, 0, "uint:4", 10, None, "keypurpose", "KEY2 purpose", None), 151 ("KEY_PURPOSE_3", "security", 0, 3, 4, "uint:4", 11, None, "keypurpose", "KEY3 purpose", None), 152 ("KEY_PURPOSE_4", "security", 0, 3, 8, "uint:4", 12, None, "keypurpose", "KEY4 purpose", None), 153 ("KEY_PURPOSE_5", "security", 0, 3, 12, "uint:4", 13, None, "keypurpose", "KEY5 purpose", None), 154 ("SECURE_BOOT_EN", "security", 0, 3, 20, "bool", 15, None, None, "Enables secure boot", None), 155 ("SECURE_BOOT_AGGRESSIVE_REVOKE", "security", 0, 3, 21, "bool", 16, None, None, "Enables aggressive secure boot key revocation mode", 156 None), 157 ("FLASH_TPUW", "flash config", 0, 3, 28, "uint:4", 18, None, None, "Configures flash startup delay after SoC power-up, " 158 "unit is (ms/2). When the value is 15, delay is 7.5 ms", 159 None), 160 ("DIS_DOWNLOAD_MODE", "security", 0, 4, 0, "bool", 18, None, None, "Disables all Download boot modes", None), 161 ("DIS_DIRECT_BOOT", "config", 0, 4, 1, "bool", 18, None, None, "Disables direct boot mode", None), 162 ("DIS_USB_SERIAL_JTAG_ROM_PRINT", "config", 0, 4, 2, "bool", 18, None, None, "Disables USB-Serial-JTAG ROM printing", None), 163 ("DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE", "usb config", 0, 4, 4, "bool", 18, None, None, "Disables USB-Serial-JTAG download feature in " 164 "UART download boot mode", None), 165 ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 4, 5, "bool", 18, None, None, "Enables secure UART download mode " 166 "(read/write flash only)", None), 167 ("UART_PRINT_CONTROL", "config", 0, 4, 6, "uint:2", 18, None, None, "Sets the default UART boot message output mode", 168 {0: "Enabled", 169 1: "Enable when GPIO8 is low at reset", 170 2: "Enable when GPIO8 is high at reset", 171 3: "Disabled"}), 172 ("FORCE_SEND_RESUME", "config", 0, 4, 13, "bool", 18, None, None, "Force ROM code to send a resume command during SPI boot" 173 "during SPI boot", None), 174 ("SECURE_VERSION", "identity", 0, 4, 14, "uint:16", 18, None, "bitcount", "Secure version (used by ESP-IDF anti-rollback feature)", 175 None), 176 ("ERR_RST_ENABLE", "config", 0, 4, 31, "bool", 19, None, None, "Use BLOCK0 to check error record registers", 177 {0: "without check", 178 1: "with check"}), 179 ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 5, 0, "bool", 19, None, None, "Disables check of wafer version major", None), 180 ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 5, 1, "bool", 19, None, None, "Disables check of blk version major", None), 181 # 182 # Table 53: Parameters in BLOCK1-10 183 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 184 ("MAC", "identity", 1, 0, 0, "bytes:6", 20, None, "mac", "Factory MAC Address", None), 185 ("SPI_PAD_CONFIG_CLK", "spi_pad_config", 1, 1, 16, "uint:6", 20, None, None, "SPI CLK pad", None), 186 ("SPI_PAD_CONFIG_Q", "spi_pad_config", 1, 1, 22, "uint:6", 20, None, None, "SPI Q (D1) pad", None), 187 ("SPI_PAD_CONFIG_D", "spi_pad_config", 1, 1, 28, "uint:6", 20, None, None, "SPI D (D0) pad", None), 188 ("SPI_PAD_CONFIG_CS", "spi_pad_config", 1, 2, 2, "uint:6", 20, None, None, "SPI CS pad", None), 189 ("SPI_PAD_CONFIG_HD", "spi_pad_config", 1, 2, 8, "uint:6", 20, None, None, "SPI HD (D3) pad", None), 190 ("SPI_PAD_CONFIG_WP", "spi_pad_config", 1, 2, 14, "uint:6", 20, None, None, "SPI WP (D2) pad", None), 191 ("SPI_PAD_CONFIG_DQS", "spi_pad_config", 1, 2, 20, "uint:6", 20, None, None, "SPI DQS pad", None), 192 ("SPI_PAD_CONFIG_D4", "spi_pad_config", 1, 2, 26, "uint:6", 20, None, None, "SPI D4 pad", None), 193 ("SPI_PAD_CONFIG_D5", "spi_pad_config", 1, 3, 0, "uint:6", 20, None, None, "SPI D5 pad", None), 194 ("SPI_PAD_CONFIG_D6", "spi_pad_config", 1, 3, 6, "uint:6", 20, None, None, "SPI D6 pad", None), 195 ("SPI_PAD_CONFIG_D7", "spi_pad_config", 1, 3, 12, "uint:6", 20, None, None, "SPI D7 pad", None), 196 197 ("WAFER_VERSION_MINOR_LO", "identity", 1, 3, 18, "uint:3", 20, None, None, "WAFER_VERSION_MINOR least significant bits", None), 198 ("PKG_VERSION", "identity", 1, 3, 21, "uint:3", 20, None, None, "Package version", None), 199 ("BLK_VERSION_MINOR", "identity", 1, 3, 24, "uint:3", 20, None, None, "BLOCK version minor", None), 200 ("WAFER_VERSION_MINOR_HI", "identity", 1, 5, 23, "uint:1", 20, None, None, "WAFER_VERSION_MINOR most significant bits", None), 201 ("WAFER_VERSION_MAJOR", "identity", 1, 5, 24, "uint:2", 20, None, None, "WAFER_VERSION_MAJOR", None), 202 203 ("OPTIONAL_UNIQUE_ID", "identity", 2, 0, 0, "bytes:16", 21, None, "keyblock", "Optional unique 128-bit ID", None), 204 ("BLK_VERSION_MAJOR", "identity", 2, 4, 0, "uint:2", 21, None, None, "BLOCK version major", 205 {0: "No calibration", 206 1: "With calibration"}), 207 ("CUSTOM_MAC", "identity", 3, 6, 8, "bytes:6", 22, None, "mac", "Custom MAC Address", None), 208 ] 209 210 KEYBLOCKS = [ 211 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 212 ('BLOCK_USR_DATA', "config", 3, 0, 0, "bytes:32", 22, None, None, "User data", None), 213 ('BLOCK_KEY0', "security", 4, 0, 0, "bytes:32", 23, 0, "keyblock", "Encryption key0 or user data", None), 214 ('BLOCK_KEY1', "security", 5, 0, 0, "bytes:32", 24, 1, "keyblock", "Encryption key1 or user data", None), 215 ('BLOCK_KEY2', "security", 6, 0, 0, "bytes:32", 25, 2, "keyblock", "Encryption key2 or user data", None), 216 ('BLOCK_KEY3', "security", 7, 0, 0, "bytes:32", 26, 3, "keyblock", "Encryption key3 or user data", None), 217 ('BLOCK_KEY4', "security", 8, 0, 0, "bytes:32", 27, 4, "keyblock", "Encryption key4 or user data", None), 218 ('BLOCK_KEY5', "security", 9, 0, 0, "bytes:32", 28, 5, "keyblock", "Encryption key5 or user data", None), 219 ('BLOCK_SYS_DATA2', "security", 10, 0, 0, "bytes:32", 29, 6, "keyblock", "System data (part 2)", None), 220 ] 221 222 # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 223 BLOCK2_CALIBRATION_EFUSES = [ 224 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 225 ('TEMP_SENSOR_CAL', "calibration", 2, 4, 7, "uint:9", 21, None, "t_sensor", "Temperature calibration", None), 226 ('ADC1_MODE0_D2', "calibration", 2, 4, 16, "uint:8", 21, None, "adc_tp", "ADC1 calibration 1", None), 227 ('ADC1_MODE1_D2', "calibration", 2, 4, 24, "uint:8", 21, None, "adc_tp", "ADC1 calibration 2", None), 228 ('ADC1_MODE2_D2', "calibration", 2, 5, 0, "uint:8", 21, None, "adc_tp", "ADC1 calibration 3", None), 229 ('ADC1_MODE3_D2', "calibration", 2, 5, 8, "uint:8", 21, None, "adc_tp", "ADC1 calibration 4", None), 230 ('ADC2_MODE0_D2', "calibration", 2, 5, 16, "uint:8", 21, None, "adc_tp", "ADC2 calibration 5", None), 231 ('ADC2_MODE1_D2', "calibration", 2, 5, 24, "uint:8", 21, None, "adc_tp", "ADC2 calibration 6", None), 232 ('ADC2_MODE2_D2', "calibration", 2, 6, 0, "uint:8", 21, None, "adc_tp", "ADC2 calibration 7", None), 233 ('ADC2_MODE3_D2', "calibration", 2, 6, 8, "uint:8", 21, None, "adc_tp", "ADC2 calibration 8", None), 234 ('ADC1_MODE0_D1', "calibration", 2, 6, 16, "uint:6", 21, None, "adc_tp", "ADC1 calibration 9", None), 235 ('ADC1_MODE1_D1', "calibration", 2, 6, 22, "uint:6", 21, None, "adc_tp", "ADC1 calibration 10", None), 236 ('ADC1_MODE2_D1', "calibration", 2, 6, 28, "uint:6", 21, None, "adc_tp", "ADC1 calibration 11", None), 237 ('ADC1_MODE3_D1', "calibration", 2, 7, 2, "uint:6", 21, None, "adc_tp", "ADC1 calibration 12", None), 238 ('ADC2_MODE0_D1', "calibration", 2, 7, 8, "uint:6", 21, None, "adc_tp", "ADC2 calibration 13", None), 239 ('ADC2_MODE1_D1', "calibration", 2, 7, 14, "uint:6", 21, None, "adc_tp", "ADC2 calibration 14", None), 240 ('ADC2_MODE2_D1', "calibration", 2, 7, 20, "uint:6", 21, None, "adc_tp", "ADC2 calibration 15", None), 241 ('ADC2_MODE3_D1', "calibration", 2, 7, 26, "uint:6", 21, None, "adc_tp", "ADC2 calibration 16", None), 242 ] 243 244 CALC = [ 245 ("WAFER_VERSION_MINOR", "identity", 0, None, None, "uint:4", None, None, "wafer", "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)", None), 246 ] 247# fmt: on 248
