1{IDF_TARGET_STRAP_BOOT_GPIO:default="GPIO0", esp32="GPIO0", esp32s2="GPIO0", esp32s3="GPIO0", esp32c3="GPIO9"} 2 3{IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO2", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46", esp32c3="GPIO8"} 4 5.. _boot-mode: 6 7Boot Mode Selection 8=================== 9 10This guide explains how to select the boot mode correctly and describes the boot log messages of {IDF_TARGET_NAME}. 11 12.. only:: esp8266 13 14 On many development boards with built-in USB/Serial, this is done for you and ``esptool`` can automatically reset the board into bootloader mode. For other configurations, you will need to follow these steps: 15 16 Required Pins 17 ------------- 18 19 The following ESP8266 pins must be in a known state for either normal (flash boot) or serial bootloader operation. Most development boards or modules make necessary connections already, internally: 20 21 +--------+--------------------------------------------------------------------------------------------------------------------+ 22 | GPIO | State | 23 +========+====================================================================================================================+ 24 | 15 | Pulled Low/GND (directly connected to GND, or external pull-down resistor) | 25 +--------+--------------------------------------------------------------------------------------------------------------------+ 26 | 2 | Pull-up resistor High/VCC, or No Connection (pin has internal weak pullup, external pullup resistor is optional) | 27 +--------+--------------------------------------------------------------------------------------------------------------------+ 28 29 If these pins are set differently to shown, nothing on the ESP8266 will work as expected. See `ESP8266 Pin List document <https://www.espressif.com/en/support/documents/technical-documents?keys=ESP8266+Pin+List>`__ to see what boot modes are enabled for different pin combinations. 30 31 When the ESP8266 goes into serial bootloader mode, the Boot ROM switches GPIO2 to an output and the UART TX signal is also output to this pin. For this reason GPIO2 should not be directly connected to VCC. Similarly, make sure GPIO2 is not connected to another peripheral where this may cause an issue when in download mode. 32 33 Select Bootloader Mode 34 ---------------------- 35 36 The ESP8266 will enter the serial bootloader when GPIO0 is held low on reset. Otherwise it will run the program in flash. 37 38 +---------------+----------------------------------------+ 39 | GPIO0 Input | Mode | 40 +===============+========================================+ 41 | Low/GND | ROM serial bootloader for esptool | 42 +---------------+----------------------------------------+ 43 | High/VCC | Normal execution mode | 44 +---------------+----------------------------------------+ 45 46 Many configurations use a "Flash" button that pulls GPIO0 low when pressed. 47 48.. only:: not esp8266 49 50 .. warning:: 51 52 The {IDF_TARGET_NAME} has a 45k ohm internal pull-up/pull-down resistor at {IDF_TARGET_STRAP_BOOT_GPIO} (and other pins). If you want to connect a switch button to enter the boot mode, this has to be a strong pull-down. For example a 10k resistor to GND. 53 54 Information about {IDF_TARGET_NAME} strapping pins can also be found in the `{IDF_TARGET_NAME} Datasheet <https://www.espressif.com/en/support/documents/technical-documents?keys={IDF_TARGET_NAME}+datasheet>`__, section "Strapping Pins". 55 56 On many development boards with built-in USB/Serial, ``esptool.py`` can automatically reset the board into bootloader mode. For other configurations or custom hardware, you will need to check the orientation of some "strapping pins" to get the correct boot mode: 57 58 Select Bootloader Mode 59 ---------------------- 60 61 {IDF_TARGET_STRAP_BOOT_GPIO} 62 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 63 64 The {IDF_TARGET_NAME} will enter the serial bootloader when {IDF_TARGET_STRAP_BOOT_GPIO} is held low on reset. Otherwise it will run the program in flash. 65 66 +---------------+----------------------------------------+ 67 | {IDF_TARGET_STRAP_BOOT_GPIO} Input | Mode | 68 +===============+========================================+ 69 | Low/GND | ROM serial bootloader for esptool | 70 +---------------+----------------------------------------+ 71 | High/VCC | Normal execution mode | 72 +---------------+----------------------------------------+ 73 74 {IDF_TARGET_STRAP_BOOT_GPIO} has an internal pullup resistor, so if it is left unconnected then it will pull high. 75 76 Many boards use a button marked "Flash" (or "BOOT" on some Espressif development boards) that pulls {IDF_TARGET_STRAP_BOOT_GPIO} low when pressed. 77 78 {IDF_TARGET_STRAP_BOOT_2_GPIO} 79 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 80 81 .. only:: not esp32c3 82 83 {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be either left unconnected/floating, or driven Low, in order to enter the serial bootloader. 84 85 .. only:: esp32c3 86 87 {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be driven High, in order to enter the serial bootloader reliably. The strapping combination of {IDF_TARGET_STRAP_BOOT_2_GPIO} = 0 and {IDF_TARGET_STRAP_BOOT_GPIO} = 0 is invalid and will trigger unexpected behavior. 88 89 In normal boot mode ({IDF_TARGET_STRAP_BOOT_GPIO} high), {IDF_TARGET_STRAP_BOOT_2_GPIO} is ignored. 90 91 92 Other Pins 93 ^^^^^^^^^^ 94 95 .. only:: not esp32 96 97 As well as the above mentioned pins, other ones influence the serial bootloader, please consult the `{IDF_TARGET_NAME} Datasheet <https://www.espressif.com/en/support/documents/technical-documents?keys={IDF_TARGET_NAME}+datasheet>`__, section "Strapping Pins". 98 99 .. only:: esp32 100 101 As well as {IDF_TARGET_STRAP_BOOT_GPIO} and {IDF_TARGET_STRAP_BOOT_2_GPIO}, the following pins influence the serial bootloader mode: 102 103 +-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 104 | GPIO | Meaning | 105 +=============+============================================================================================================================================================================================================================================================================================+ 106 | 12 (MTDI) | If driven High, flash voltage (VDD_SDIO) is 1.8V not default 3.3V. Has internal pull-down, so unconnected = Low = 3.3V. May prevent flashing and/or booting if 3.3V flash is used and this pin is pulled high, causing the flash to brownout. See the datasheet for more details. | 107 +-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 108 | 15 (MTDO) | If driven Low, silences boot messages printed by the ROM bootloader. Has an internal pull-up, so unconnected = High = normal output. | 109 +-------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 110 111 For more information, consult the `{IDF_TARGET_NAME} Datasheet <https://www.espressif.com/en/support/documents/technical-documents?keys={IDF_TARGET_NAME}+datasheet>`__, section "Strapping Pins". 112 113.. _automatic-bootloader: 114 115Automatic Bootloader 116-------------------- 117 118``esptool.py`` resets {IDF_TARGET_NAME} automatically by asserting ``DTR`` and ``RTS`` control lines of the USB to serial converter chip, i.e., FTDI, CP210x, or CH340x. The ``DTR`` and ``RTS`` control lines are in turn connected to ``{IDF_TARGET_STRAP_BOOT_GPIO}`` and ``EN`` (``CHIP_PU``) pins of {IDF_TARGET_NAME}, thus changes in the voltage levels of ``DTR`` and ``RTS`` will boot the {IDF_TARGET_NAME} into Firmware Download mode. 119 120.. note:: 121 122 When developing ``esptool.py``, keep in mind ``DTR`` and ``RTS`` are active low signals, i.e., ``True`` = pin @ 0V, ``False`` = pin @ VCC. 123 124As an example of auto-reset curcuitry implementation, check the `schematic <https://dl.espressif.com/dl/schematics/esp32_devkitc_v4-sch-20180607a.pdf>`_ of the ESP32 DevKitC development board: 125 126- The **Micro USB 5V & USB-UART** section shows the ``DTR`` and ``RTS`` control lines of the USB to serial converter chip connected to ``GPIO0`` and ``EN`` pins of the ESP module. 127- Some OS and/or drivers may activate ``RTS`` and or ``DTR`` automatically when opening the serial port (true only for some serial terminal programs, not ``esptool.py``), pulling them low together and holding the ESP in reset. If ``RTS`` is wired directly to ``EN`` then RTS/CTS "hardware flow control" needs to be disabled in the serial program to avoid this. 128 An additional circuitry is implemented in order to avoid this problem - if both ``RTS`` and ``DTR`` are asserted together, this doesn't reset the chip. The schematic shows this specific circuit with two transistors and its truth table. 129- If this circuitry is implemented (all Espressif boards have it), adding a capacitor between the ``EN`` pin and ``GND`` (in the 1uF-10uF range) is necessary for the reset circuitry to work reliably. This is shown in the **ESP32 Module** section of the schematic. 130- The **Switch Button** section shows buttons needed for :ref:`manually switching to bootloader <manual-bootloader>`. 131 132Make the following connections for ``esptool`` to automatically enter the bootloader of an {IDF_TARGET_NAME} chip: 133 134+-------------+--------------+ 135| ESP Pin | Serial Pin | 136+=============+==============+ 137| EN | RTS | 138+-------------+--------------+ 139| {IDF_TARGET_STRAP_BOOT_GPIO} | DTR | 140+-------------+--------------+ 141 142In Linux serial ports by default will assert RTS when nothing is attached to them. This can hold the {IDF_TARGET_NAME} in a reset loop which may cause some serial adapters to subsequently reset loop. This functionality can be disabled by disabling ``HUPCL`` (ie ``sudo stty -F /dev/ttyUSB0 -hupcl``). 143 144(Some third party {IDF_TARGET_NAME} development boards use an automatic reset circuit for ``EN`` & ``{IDF_TARGET_STRAP_BOOT_GPIO}`` pins, but don't add a capacitor on the ``EN`` pin. This results in unreliable automatic reset, especially on Windows. Adding a 1uF (or higher) value capacitor between ``EN`` pin and ``GND`` may make automatic reset more reliable.) 145 146In general, you should have no problems with the official Espressif development boards. However, ``esptool.py`` is not able to reset your hardware automatically in the following cases: 147 148- Your hardware does not have the ``DTR`` and ``RTS`` lines connected to ``{IDF_TARGET_STRAP_BOOT_GPIO}`` and ``EN`` (``CHIP_PU``) 149- The ``DTR`` and ``RTS`` lines are configured differently 150- There are no such serial control lines at all 151 152.. _manual-bootloader: 153 154Manual Bootloader 155----------------- 156 157Depending on the kind of hardware you have, it may also be possible to manually put your {IDF_TARGET_NAME} board into Firmware Download mode (reset). 158 159- For development boards produced by Espressif, this information can be found in the respective getting started guides or user guides. For example, to manually reset a development board, hold down the **Boot** button (``{IDF_TARGET_STRAP_BOOT_GPIO}``) and press the **EN** button (``EN`` (``CHIP_PU``)). 160- For other types of hardware, try pulling ``{IDF_TARGET_STRAP_BOOT_GPIO}`` down. 161 162.. only:: esp8266 163 164 .. _boot-log-esp8266: 165 166 Boot Log 167 -------- 168 169 The ESP8266 boot rom writes a log to the UART when booting. The timing is a little bit unusual: ``74880 baud`` (see :ref:`serial-port-settings`). 170 171 :: 172 173 ets Jan 8 2014,rst cause 1, boot mode:(3,7) 174 175 load 0x40100000, len 24236, room 16 176 tail 12 177 chksum 0xb7 178 ho 0 tail 12 room 4 179 load 0x3ffe8000, len 3008, room 12 180 tail 4 181 chksum 0x2c 182 load 0x3ffe8bc0, len 4816, room 4 183 tail 12 184 chksum 0x46 185 csum 0x46 186 187 188 Explanation 189 ^^^^^^^^^^^ 190 191 **rst_cause:** 192 193 +---------------+----------------------------------------+ 194 | Value | Meaning | 195 +===============+========================================+ 196 | 1 | power-on | 197 +---------------+----------------------------------------+ 198 | 2 | external-reset | 199 +---------------+----------------------------------------+ 200 | 4 | hardware watchdog-reset | 201 +---------------+----------------------------------------+ 202 203 204 **The first parameter of boot_mode:** 205 206 +-------------------------+----------------------------------------------+ 207 | Value | Meaning | 208 +=========================+==============================================+ 209 | 1 (eg. boot mode:(1,x)) | UART download mode (download FW into Flash) | 210 +-------------------------+----------------------------------------------+ 211 | 2 (eg. boot mode:(3,x)) | Boot from flash mode | 212 +-------------------------+----------------------------------------------+ 213 214 **chksum:** 215 216 If value of “chksum” == value of “csum”, it means flash has been read correctly during booting. 217 218 The rest of boot messages are used internally by Espressif. 219 220.. only:: esp32 221 222 Boot Log 223 -------- 224 225 Boot Mode Message 226 ^^^^^^^^^^^^^^^^^ 227 228 After reset, the second line printed by the ESP32 ROM (at 115200bps) is a reset & boot mode message: 229 230 :: 231 232 ets Jun 8 2016 00:22:57 233 rst:0x1 (POWERON_RESET),boot:0x3 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2)) 234 235 ``rst:0xNN (REASON)`` is an enumerated value (and description) of the reason for the reset. `A mapping between the hex value and each reason can be found in the ESP-IDF source <https://github.com/espressif/esp-idf/blob/release/v3.0/components/esp32/include/rom/rtc.h#L80>`__. 236 The value can be read in ESP32 code via the `get_reset_reason() ROM function <https://github.com/espressif/esp-idf/blob/release/v3.0/components/esp32/include/rom/rtc.h#L147>`__. 237 238 ``boot:0xNN (DESCRIPTION)`` is the hex value of the strapping pins, as represented in the `GPIO_STRAP register <https://github.com/espressif/esp-idf/blob/3cad00fdcca7dd4b7939d7862407c000c29657c1/components/soc/esp32/include/soc/gpio_reg.h#L130>`__. 239 The individual bit values are as follows: 240 241 - ``0x01`` - GPIO5 242 - ``0x02`` - MTDO (GPIO15) 243 - ``0x04`` - GPIO4 244 - ``0x08`` - GPIO2 245 - ``0x10`` - GPIO0 246 - ``0x20`` - MTDI (GPIO12) 247 248 If the pin was high on reset, the bit value will be set. If it was low on reset, the bit will be cleared. 249 250 A number of boot mode strings can be shown depending on which bits are set: 251 252 - ``DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2)`` - ESP32 is in download flashing mode (suitable for esptool) 253 - ``SPI_FAST_FLASH_BOOT`` - This is the normal SPI flash boot mode. 254 - Other modes (including ``HSPI_FLASH_BOOT``, ``SPI_FLASH_BOOT``, ``SDIO_REI_FEO_V1_BOOT``, ``ATE_BOOT``) may be shown here. This indicates an unsupported boot mode has been selected. 255 Consult the strapping pins shown above (in most cases, one of these modes is selected if GPIO2 has been pulled high when GPIO0 is low). 256 257 .. note:: 258 259 ``GPIO_STRAP`` register includes GPIO 4 but this pin is not used by any supported boot mode and be set either high or low for all supported boot modes. 260 261 Later Boot Messages 262 ^^^^^^^^^^^^^^^^^^^ 263 264 Later output from the ROM bootloader depends on the strapping pins and 265 the boot mode. Some common output includes: 266 267 Early Flash Read Error 268 """""""""""""""""""""" 269 270 :: 271 272 flash read err, 1000 273 274 This fatal error indicates that the bootloader tried to read the software bootloader header at address 0x1000 but failed to read valid data. Possible reasons for this include: 275 276 - There isn't actually a bootloader at offset 0x1000 (maybe the bootloader was flashed to the wrong offset by mistake, or the flash has been erased and no bootloader has been flashed yet.) 277 - Physical problem with the connection to the flash chip, or flash chip power. 278 - Boot mode accidentally set to ``HSPI_FLASH_BOOT``, which uses different SPI flash pins. Check GPIO2 (see above). 279 - VDDSDIO has been enabled at 1.8V (due to MTDI/GPIO12, see above), but this flash chip requires 3.3V so it's browning out. 280 - Flash encryption is enabled but the bootloader is plaintext. Alternatively, flash encryption is disabled but the bootloader is encrypted ciphertext. 281 282 Software Bootloader Header Info 283 """"""""""""""""""""""""""""""" 284 285 :: 286 287 configsip: 0, SPIWP:0x00 288 clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 289 mode:DIO, clock div:1 290 291 This is normal boot output based on a combination of efuse values and information read from the bootloader header at flash offset 0x1000: 292 293 - ``configsip: N`` indicates SPI flash config: 294 - 0 for default SPI flash 295 - 1 if booting from the HSPI bus (due to EFUSE configuration) 296 - Any other value indicates that SPI flash pins have been remapped via efuse (the value is the value read from efuse, consult :ref:`espefuse docs <espefuse>` to get an easier to read representation of these pin mappings). 297 - ``SPIWP:0xNN`` indicates a custom ``WP`` pin value, which is stored in the bootloader header. This pin value is only used if SPI flash pins have been remapped via efuse (as shown in the ``configsip`` value). 298 All custom pin values but WP are encoded in the configsip byte loaded from efuse, and WP is supplied in the bootloader header. 299 - ``clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00`` Custom GPIO drive strength values for SPI flash pins. These are read from the bootloader header in flash. Not currently supported. 300 - ``mode: AAA, clock div: N``. SPI flash access mode. Read from the bootloader header, correspond to the ``--flash_mode`` and ``--flash_freq`` arguments supplied to ``esptool.py write_flash`` or ``esptool.py elf2image``. 301 - ``mode`` can be DIO, DOUT, QIO, or QOUT. *QIO and QOUT are not supported here*, to boot in a Quad I/O mode the ROM bootloader should load the software bootloader in a Dual I/O mode and then the ESP-IDF software bootloader enables Quad I/O based on the detected flash chip mode. 302 - ``clock div: N`` is the SPI flash clock frequency divider. This is an integer clock divider value from an 80MHz APB clock, based on the supplied ``--flash_freq`` argument (ie 80MHz=1, 40MHz=2, etc). 303 The ROM bootloader actually loads the software bootloader at a lower frequency than the flash_freq value. The initial APB clock frequency is equal to the crystal frequency, so with a 40MHz crystal the SPI clock used to load the software bootloader will be half the configured value (40MHz/2=20MHz). 304 When the software bootloader starts it sets the APB clock to 80MHz causing the SPI clock frequency to match the value set when flashing. 305 306 Software Bootloader Load Segments 307 """"""""""""""""""""""""""""""""" 308 309 :: 310 311 load:0x3fff0008,len:8 312 load:0x3fff0010,len:3680 313 load:0x40078000,len:8364 314 load:0x40080000,len:252 315 entry 0x40080034 316 317 These entries are printed as the ROM bootloader loads each segment in the software bootloader image. The load address and length of each segment is printed. 318 319 You can compare these values to the software bootloader image by running ``esptool.py --chip esp32 image_info /path/to/bootloader.bin`` to dump image info including a summary of each segment. Corresponding details will also be found in the bootloader ELF file headers. 320 321 If there is a problem with the SPI flash chip addressing mode, the values printed by the bootloader here may be corrupted. 322 323 The final line shows the entry point address of the software bootloader, where the ROM bootloader will call as it hands over control. 324
