1
2 // Copyright 2018 Espressif Systems (Shanghai) PTE LTD
3 //
4 // Licensed under the Apache License, Version 2.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
7 //
8 // http://www.apache.org/licenses/LICENSE-2.0
9 //
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
15
16 #include <string.h>
17 #include "sdkconfig.h"
18 #include "esp_system.h"
19 #include "esp_private/system_internal.h"
20 #include "esp_attr.h"
21 #include "esp_log.h"
22 #include "esp_rom_uart.h"
23 #include "soc/dport_reg.h"
24 #include "soc/gpio_reg.h"
25 #include "soc/rtc_cntl_reg.h"
26 #include "soc/timer_group_reg.h"
27 #include "soc/cpu.h"
28 #include "soc/rtc.h"
29 #include "soc/syscon_reg.h"
30 #include "soc/rtc_periph.h"
31 #include "hal/wdt_hal.h"
32 #include "freertos/xtensa_api.h"
33
34 #include "esp32s3/rom/cache.h"
35 #include "esp32s3/rom/rtc.h"
36
37 /* "inner" restart function for after RTOS, interrupts & anything else on this
38 * core are already stopped. Stalls other core, resets hardware,
39 * triggers restart.
40 */
esp_restart_noos(void)41 void IRAM_ATTR esp_restart_noos(void)
42 {
43 // Disable interrupts
44 xt_ints_off(0xFFFFFFFF);
45
46 // Enable RTC watchdog for 1 second
47 wdt_hal_context_t rtc_wdt_ctx;
48 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
49 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
50 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
51 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
52 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
53 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
54 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
55 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
56
57
58 // Disable TG0/TG1 watchdogs
59 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
60 wdt_hal_write_protect_disable(&wdt0_context);
61 wdt_hal_disable(&wdt0_context);
62 wdt_hal_write_protect_enable(&wdt0_context);
63
64 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
65 wdt_hal_write_protect_disable(&wdt1_context);
66 wdt_hal_disable(&wdt1_context);
67 wdt_hal_write_protect_enable(&wdt1_context);
68
69 // Flush any data left in UART FIFOs
70 esp_rom_uart_tx_wait_idle(0);
71 esp_rom_uart_tx_wait_idle(1);
72 // Disable cache
73 Cache_Disable_ICache();
74 Cache_Disable_DCache();
75
76 // Reset and stall the other CPU.
77 // CPU must be reset before stalling, in case it was running a s32c1i
78 // instruction. This would cause memory pool to be locked by arbiter
79 // to the stalled CPU, preventing current CPU from accessing this pool.
80 const uint32_t core_id = cpu_hal_get_core_id();
81 #if !CONFIG_FREERTOS_UNICORE
82 const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
83 esp_cpu_reset(other_core_id);
84 esp_cpu_stall(other_core_id);
85 #endif
86
87 // 2nd stage bootloader reconfigures SPI flash signals.
88 // Reset them to the defaults expected by ROM.
89 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
90 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
91 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
92 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
93 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
94 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
95
96 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
97 SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
98 SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST |
99 SYSTEM_BT_RST | SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST |
100 SYSTEM_SDIO_HOST_RST | SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
101 SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST | SYSTEM_BB_REG_RST);
102 REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
103
104 // Reset timer/spi/uart
105 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
106 SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
107 REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
108
109 // Reset dma
110 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
111 REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
112
113 SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
114 CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
115
116 // Set CPU back to XTAL source, no PLL, same as hard reset
117 #if !CONFIG_IDF_ENV_FPGA
118 rtc_clk_cpu_freq_set_xtal();
119 #endif
120
121 #if !CONFIG_FREERTOS_UNICORE
122 // Clear entry point for APP CPU
123 REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
124 #endif
125
126 // Reset CPUs
127 if (core_id == 0) {
128 // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
129 #if !CONFIG_FREERTOS_UNICORE
130 esp_cpu_reset(1);
131 #endif
132 esp_cpu_reset(0);
133 }
134 #if !CONFIG_FREERTOS_UNICORE
135 else {
136 // Running on APP CPU: need to reset PRO CPU and unstall it,
137 // then reset APP CPU
138 esp_cpu_reset(0);
139 esp_cpu_unstall(0);
140 esp_cpu_reset(1);
141 }
142 #endif
143 while (true) {
144 ;
145 }
146 }
147
