1 // Copyright 2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <string.h>
16 #include "sdkconfig.h"
17 #include "esp_system.h"
18 #include "esp_private/system_internal.h"
19 #include "esp_attr.h"
20 #include "esp_efuse.h"
21 #include "esp_log.h"
22 #include "riscv/riscv_interrupts.h"
23 #include "riscv/interrupt.h"
24 #include "esp_rom_uart.h"
25 #include "soc/gpio_reg.h"
26 #include "soc/rtc_cntl_reg.h"
27 #include "soc/timer_group_reg.h"
28 #include "soc/cpu.h"
29 #include "soc/rtc.h"
30 #include "soc/rtc_periph.h"
31 #include "soc/syscon_reg.h"
32 #include "soc/system_reg.h"
33 #include "hal/wdt_hal.h"
34 #include "cache_err_int.h"
35
36 #include "esp32h2/rom/cache.h"
37 #include "esp32h2/rom/rtc.h"
38
39 /* "inner" restart function for after RTOS, interrupts & anything else on this
40 * core are already stopped. Stalls other core, resets hardware,
41 * triggers restart.
42 */
esp_restart_noos(void)43 void IRAM_ATTR esp_restart_noos(void)
44 {
45 // Disable interrupts
46 riscv_global_interrupts_disable();
47 // Enable RTC watchdog for 1 second
48 wdt_hal_context_t rtc_wdt_ctx;
49 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
50 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
51 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
52 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
53 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
54 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
55 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
56 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
57
58 // Reset and stall the other CPU.
59 // CPU must be reset before stalling, in case it was running a s32c1i
60 // instruction. This would cause memory pool to be locked by arbiter
61 // to the stalled CPU, preventing current CPU from accessing this pool.
62 const uint32_t core_id = cpu_hal_get_core_id();
63 #if !CONFIG_FREERTOS_UNICORE
64 const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
65 esp_cpu_reset(other_core_id);
66 esp_cpu_stall(other_core_id);
67 #endif
68
69 // Disable TG0/TG1 watchdogs
70 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
71 wdt_hal_write_protect_disable(&wdt0_context);
72 wdt_hal_disable(&wdt0_context);
73 wdt_hal_write_protect_enable(&wdt0_context);
74
75 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
76 wdt_hal_write_protect_disable(&wdt1_context);
77 wdt_hal_disable(&wdt1_context);
78 wdt_hal_write_protect_enable(&wdt1_context);
79
80 // Flush any data left in UART FIFOs
81 esp_rom_uart_tx_wait_idle(0);
82 esp_rom_uart_tx_wait_idle(1);
83 // Disable cache
84 Cache_Disable_ICache();
85
86 // 2nd stage bootloader reconfigures SPI flash signals.
87 // Reset them to the defaults expected by ROM.
88 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
89 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
90 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
91 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
92 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
93 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
94
95 // Reset timer/spi/uart
96 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
97 SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
98 REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
99 // Reset dma
100 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
101 REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
102
103 // Set CPU back to XTAL source, no PLL, same as hard reset
104 #if !CONFIG_IDF_ENV_FPGA
105 rtc_clk_cpu_freq_set_xtal();
106 #endif
107
108 #if !CONFIG_FREERTOS_UNICORE
109 // Clear entry point for APP CPU
110 REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
111 #endif
112
113 // Reset CPUs
114 if (core_id == 0) {
115 // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
116 #if !CONFIG_FREERTOS_UNICORE
117 esp_cpu_reset(1);
118 #endif
119 esp_cpu_reset(0);
120 }
121 #if !CONFIG_FREERTOS_UNICORE
122 else {
123 // Running on APP CPU: need to reset PRO CPU and unstall it,
124 // then reset APP CPU
125 esp_cpu_reset(0);
126 esp_cpu_unstall(0);
127 esp_cpu_reset(1);
128 }
129 #endif
130 while (true) {
131 ;
132 }
133 }
134
