1 // Copyright 2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <string.h>
16 #include "esp_system.h"
17 #include "esp_private/system_internal.h"
18 #include "esp_attr.h"
19 #include "esp_efuse.h"
20 #include "esp_log.h"
21 #include "esp_ipc_isr.h"
22 #include "sdkconfig.h"
23 #include "esp_rom_uart.h"
24 #include "soc/dport_reg.h"
25 #include "soc/gpio_periph.h"
26 #include "soc/efuse_periph.h"
27 #include "soc/rtc_periph.h"
28 #include "soc/timer_periph.h"
29 #include "soc/cpu.h"
30 #include "soc/rtc.h"
31 #include "hal/wdt_hal.h"
32 #include "hal/cpu_hal.h"
33 #include "freertos/xtensa_api.h"
34 #include "soc/soc_memory_layout.h"
35 #include "cache_err_int.h"
36
37 #include "esp32/rom/cache.h"
38 #include "esp32/rom/rtc.h"
39
40 /* "inner" restart function for after RTOS, interrupts & anything else on this
41 * core are already stopped. Stalls other core, resets hardware,
42 * triggers restart.
43 */
esp_restart_noos(void)44 void IRAM_ATTR esp_restart_noos(void)
45 {
46 // Disable interrupts
47 xt_ints_off(0xFFFFFFFF);
48
49 // Enable RTC watchdog for 1 second
50 wdt_hal_context_t rtc_wdt_ctx;
51 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
52 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
53 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
54 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
55 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
56
57 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
58 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
59
60 // Reset and stall the other CPU.
61 // CPU must be reset before stalling, in case it was running a s32c1i
62 // instruction. This would cause memory pool to be locked by arbiter
63 // to the stalled CPU, preventing current CPU from accessing this pool.
64 const uint32_t core_id = cpu_hal_get_core_id();
65 const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
66 esp_cpu_reset(other_core_id);
67 esp_cpu_stall(other_core_id);
68
69 // Other core is now stalled, can access DPORT registers directly
70 esp_ipc_isr_stall_abort();
71
72 //Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
73 // Disable TG0/TG1 watchdogs
74 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
75 wdt_hal_write_protect_disable(&wdt0_context);
76 wdt_hal_disable(&wdt0_context);
77 wdt_hal_write_protect_enable(&wdt0_context);
78
79 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
80 wdt_hal_write_protect_disable(&wdt1_context);
81 wdt_hal_disable(&wdt1_context);
82 wdt_hal_write_protect_enable(&wdt1_context);
83
84 // Flush any data left in UART FIFOs
85 esp_rom_uart_tx_wait_idle(0);
86 esp_rom_uart_tx_wait_idle(1);
87 esp_rom_uart_tx_wait_idle(2);
88
89 #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
90 if (esp_ptr_external_ram(esp_cpu_get_sp())) {
91 // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
92 // then need to switch SP to Internal Memory otherwise
93 // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
94 uint32_t new_sp = SOC_DRAM_LOW + (SOC_DRAM_HIGH - SOC_DRAM_LOW) / 2;
95 SET_STACK(new_sp);
96 }
97 #endif
98
99 // Disable cache
100 Cache_Read_Disable(0);
101 Cache_Read_Disable(1);
102
103 // 2nd stage bootloader reconfigures SPI flash signals.
104 // Reset them to the defaults expected by ROM.
105 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
106 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
107 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
108 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
109 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
110 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
111
112 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
113 DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
114 DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
115 DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
116 DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
117 DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
118 DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
119
120 // Reset timer/spi/uart
121 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
122 //UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
123 DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
124 DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
125
126 // Set CPU back to XTAL source, no PLL, same as hard reset
127 rtc_clk_cpu_freq_set_xtal();
128
129 // Clear entry point for APP CPU
130 DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
131
132 // Reset CPUs
133 if (core_id == 0) {
134 // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
135 esp_cpu_reset(1);
136 esp_cpu_reset(0);
137 } else {
138 // Running on APP CPU: need to reset PRO CPU and unstall it,
139 // then reset APP CPU
140 esp_cpu_reset(0);
141 esp_cpu_unstall(0);
142 esp_cpu_reset(1);
143 }
144 while(true) {
145 ;
146 }
147 }
148
